patch-2.3.13 linux/arch/sparc64/lib/VISsave.S

• Lines: 96
• Date: Mon Aug 2 22:07:16 1999
• Orig file: v2.3.12/linux/arch/sparc64/lib/VISsave.S
• Orig date: Tue Oct 27 09:52:20 1998

diff -u --recursive --new-file v2.3.12/linux/arch/sparc64/lib/VISsave.S linux/arch/sparc64/lib/VISsave.S
@@ -1,4 +1,4 @@
-/* $Id: VISsave.S,v 1.3 1998/10/21 10:36:39 jj Exp $
+/* $Id: VISsave.S,v 1.4 1999/07/30 09:35:37 davem Exp $
  * VISsave.S: Code for saving FPU register state for
  *            VIS routines. One should not call this directly,
  *            but use macros provided in <asm/visasm.h>.
@@ -19,35 +19,35 @@
 
 	.align		32
 VISenter:
-	ldub		[%g6 + AOFF_task_tss + AOFF_thread_fpdepth], %g1
+	ldub		[%g6 + AOFF_task_thread + AOFF_thread_fpdepth], %g1
 	brnz,a,pn	%g1, 1f
 	 cmp		%g1, 1
-	stb		%g0, [%g6 + AOFF_task_tss + AOFF_thread_fpsaved]
-	stx		%fsr, [%g6 + AOFF_task_tss + AOFF_thread_xfsr]
+	stb		%g0, [%g6 + AOFF_task_thread + AOFF_thread_fpsaved]
+	stx		%fsr, [%g6 + AOFF_task_thread + AOFF_thread_xfsr]
 9:	jmpl		%g7 + %g0, %g0
 	 nop
 1:	bne,pn		%icc, 2f
 
 	 srl		%g1, 1, %g1
-vis1:	ldub		[%g6 + AOFF_task_tss + AOFF_thread_fpsaved], %g3
-	stx		%fsr, [%g6 + AOFF_task_tss + AOFF_thread_xfsr]
+vis1:	ldub		[%g6 + AOFF_task_thread + AOFF_thread_fpsaved], %g3
+	stx		%fsr, [%g6 + AOFF_task_thread + AOFF_thread_xfsr]
 	or		%g3, %o5, %g3
-	stb		%g3, [%g6 + AOFF_task_tss + AOFF_thread_fpsaved]
+	stb		%g3, [%g6 + AOFF_task_thread + AOFF_thread_fpsaved]
 	rd		%gsr, %g3
 	clr		%g1
 	ba,pt		%xcc, 3f
 
-	 stb		%g3, [%g6 + AOFF_task_tss + AOFF_thread_gsr]
+	 stb		%g3, [%g6 + AOFF_task_thread + AOFF_thread_gsr]
 2:	add		%g6, %g1, %g3
 	cmp		%o5, FPRS_DU
 	be,pn		%icc, 6f
 	 sll		%g1, 3, %g1
-	stb		%o5, [%g3 + AOFF_task_tss + AOFF_thread_fpsaved]
+	stb		%o5, [%g3 + AOFF_task_thread + AOFF_thread_fpsaved]
 	rd		%gsr, %g2
-	stb		%g2, [%g3 + AOFF_task_tss + AOFF_thread_gsr]
+	stb		%g2, [%g3 + AOFF_task_thread + AOFF_thread_gsr]
 
 	add		%g6, %g1, %g2
-	stx		%fsr, [%g2 + AOFF_task_tss + AOFF_thread_xfsr]
+	stx		%fsr, [%g2 + AOFF_task_thread + AOFF_thread_xfsr]
 	sll		%g1, 5, %g1
 3:	andcc		%o5, FPRS_DL|FPRS_DU, %g0
 	be,pn		%icc, 9b
@@ -69,10 +69,10 @@
 	jmpl		%g7 + %g0, %g0
 	 nop
 
-6:	ldub		[%g3 + AOFF_task_tss + AOFF_thread_fpsaved], %o5
+6:	ldub		[%g3 + AOFF_task_thread + AOFF_thread_fpsaved], %o5
 	or		%o5, FPRS_DU, %o5
 	add		%g6, AOFF_task_fpregs+0x80, %g2
-	stb		%o5, [%g3 + AOFF_task_tss + AOFF_thread_fpsaved]
+	stb		%o5, [%g3 + AOFF_task_thread + AOFF_thread_fpsaved]
 
 	sll		%g1, 5, %g1
 	add		%g6, AOFF_task_fpregs+0xc0, %g3
@@ -87,11 +87,11 @@
 
 	.align		32
 VISenterhalf:
-	ldub		[%g6 + AOFF_task_tss + AOFF_thread_fpdepth], %g1
+	ldub		[%g6 + AOFF_task_thread + AOFF_thread_fpdepth], %g1
 	brnz,a,pn	%g1, 1f
 	 cmp		%g1, 1
-	stb		%g0, [%g6 + AOFF_task_tss + AOFF_thread_fpsaved]
-	stx		%fsr, [%g6 + AOFF_task_tss + AOFF_thread_xfsr]
+	stb		%g0, [%g6 + AOFF_task_thread + AOFF_thread_fpsaved]
+	stx		%fsr, [%g6 + AOFF_task_thread + AOFF_thread_xfsr]
 	clr		%o5
 	jmpl		%g7 + %g0, %g0
 	 wr		%g0, FPRS_FEF, %fprs
@@ -103,12 +103,12 @@
 2:	addcc		%g6, %g1, %g3
 	sll		%g1, 3, %g1
 	andn		%o5, FPRS_DU, %g2
-	stb		%g2, [%g3 + AOFF_task_tss + AOFF_thread_fpsaved]
+	stb		%g2, [%g3 + AOFF_task_thread + AOFF_thread_fpsaved]
 
 	rd		%gsr, %g2
-	stb		%g2, [%g3 + AOFF_task_tss + AOFF_thread_gsr]
+	stb		%g2, [%g3 + AOFF_task_thread + AOFF_thread_gsr]
 	add		%g6, %g1, %g2
-	stx		%fsr, [%g2 + AOFF_task_tss + AOFF_thread_xfsr]
+	stx		%fsr, [%g2 + AOFF_task_thread + AOFF_thread_xfsr]
 	sll		%g1, 5, %g1
 3:	andcc		%o5, FPRS_DL, %g0
 	be,pn		%icc, 4f