patch-2.3.14 linux/include/asm-alpha/core_t2.h

• Lines: 334
• Date: Mon Aug 16 10:33:58 1999
• Orig file: v2.3.13/linux/include/asm-alpha/core_t2.h
• Orig date: Sun Dec 27 15:21:50 1998

diff -u --recursive --new-file v2.3.13/linux/include/asm-alpha/core_t2.h linux/include/asm-alpha/core_t2.h
@@ -78,33 +78,33 @@
  3.8fff.ffff
  *
  *  +--------------+ 3 8000 0000
- *  | CPU 0 CSRs   |            
+ *  | CPU 0 CSRs   |
  *  +--------------+ 3 8100 0000
- *  | CPU 1 CSRs   |            
+ *  | CPU 1 CSRs   |
  *  +--------------+ 3 8200 0000
- *  | CPU 2 CSRs   |            
+ *  | CPU 2 CSRs   |
  *  +--------------+ 3 8300 0000
- *  | CPU 3 CSRs   |            
+ *  | CPU 3 CSRs   |
  *  +--------------+ 3 8400 0000
- *  | CPU Reserved |            
+ *  | CPU Reserved |
  *  +--------------+ 3 8700 0000
- *  | Mem Reserved |            
+ *  | Mem Reserved |
  *  +--------------+ 3 8800 0000
- *  | Mem 0 CSRs   |            
+ *  | Mem 0 CSRs   |
  *  +--------------+ 3 8900 0000
- *  | Mem 1 CSRs   |            
+ *  | Mem 1 CSRs   |
  *  +--------------+ 3 8a00 0000
- *  | Mem 2 CSRs   |            
+ *  | Mem 2 CSRs   |
  *  +--------------+ 3 8b00 0000
- *  | Mem 3 CSRs   |            
- *  +--------------+ 3 8c00 0000           
- *  | Mem Reserved |            
- *  +--------------+ 3 8e00 0000           
- *  | PCI Bridge   |            
- *  +--------------+ 3 8f00 0000           
- *  | Expansion IO |            
- *  +--------------+ 3 9000 0000           
- *                                              
+ *  | Mem 3 CSRs   |
+ *  +--------------+ 3 8c00 0000
+ *  | Mem Reserved |
+ *  +--------------+ 3 8e00 0000
+ *  | PCI Bridge   |
+ *  +--------------+ 3 8f00 0000
+ *  | Expansion IO |
+ *  +--------------+ 3 9000 0000
+ *
  *
  */
 #define T2_CPU0_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x380000000L)
@@ -176,7 +176,7 @@
 	unsigned long	elfmc_bc_tag;	/* Backup Cache Tag Probe Results. */
 };
 
-/* 
+/*
  * Sable processor specific Machine Check Data segment.
  */
 
@@ -184,7 +184,7 @@
 	unsigned int	elfl_size;	/* size in bytes of logout area. */
 	int		elfl_sbz1:31;	/* Should be zero. */
 	char		elfl_retry:1;	/* Retry flag. */
-        unsigned int	elfl_procoffset; /* Processor-specific offset. */
+	unsigned int	elfl_procoffset; /* Processor-specific offset. */
 	unsigned int	elfl_sysoffset;	 /* Offset of system-specific. */
 	unsigned int	elfl_error_type;	/* PAL error type code. */
 	unsigned int	elfl_frame_rev;		/* PAL Frame revision. */
@@ -233,7 +233,7 @@
  */
 struct el_t2_data_other_cpu {
 	short	      elco_cpuid;	/* CPU ID */
-	short	      elco_res02[3];	
+	short	      elco_res02[3];
 	unsigned long elco_bcc;	/* CSR 0 */
 	unsigned long elco_bcce;	/* CSR 1 */
 	unsigned long elco_bccea;	/* CSR 2 */
@@ -256,7 +256,7 @@
  * Sable other CPU error frame - sable pfms section 3.44
  */
 struct el_t2_data_t2{
-        struct el_t2_frame_header elct_hdr;	/* ID$T2-FRAME */
+	struct el_t2_frame_header elct_hdr;	/* ID$T2-FRAME */
 	unsigned long elct_iocsr;	/* IO Control and Status Register */
 	unsigned long elct_cerr1;	/* Cbus Error Register 1 */
 	unsigned long elct_cerr2;	/* Cbus Error Register 2 */
@@ -294,31 +294,31 @@
 	unsigned long elcpb_bc_tag;
 };
 
-/* 
+/*
  * Sable error log data structure
  * Note there are 4 memory slots on sable (see t2.h)
  */
 struct el_t2_frame_mcheck {
-        struct el_t2_frame_header elfmc_header;	/* ID$P-FRAME_MCHECK */
+	struct el_t2_frame_header elfmc_header;	/* ID$P-FRAME_MCHECK */
 	struct el_t2_logout_header elfmc_hdr;
 	struct el_t2_procdata_mcheck elfmc_procdata;
 	struct el_t2_sysdata_mcheck elfmc_sysdata;
 	struct el_t2_data_t2 elfmc_t2data;
-	struct el_t2_data_memory elfmc_memdata[4]; 
-        struct el_t2_frame_header elfmc_footer;	/* empty */
+	struct el_t2_data_memory elfmc_memdata[4];
+	struct el_t2_frame_header elfmc_footer;	/* empty */
 };
 
 
-/* 
+/*
  * Sable error log data structures on memory errors
  */
 struct el_t2_frame_corrected {
-        struct el_t2_frame_header elfcc_header;	/* ID$P-BC-COR */
+	struct el_t2_frame_header elfcc_header;	/* ID$P-BC-COR */
 	struct el_t2_logout_header elfcc_hdr;
-	struct el_t2_data_corrected elfcc_procdata; 
+	struct el_t2_data_corrected elfcc_procdata;
 /*	struct el_t2_data_t2 elfcc_t2data;		*/
 /*	struct el_t2_data_memory elfcc_memdata[4];	*/
-        struct el_t2_frame_header elfcc_footer;	/* empty */
+	struct el_t2_frame_header elfcc_footer;	/* empty */
 };
 
 
@@ -398,10 +398,9 @@
 
 
 /*
- * Memory functions.  64-bit and 32-bit accesses are done through
- * dense memory space, everything else through sparse space.
- * 
- * For reading and writing 8 and 16 bit quantities we need to 
+ * Memory functions.
+ *
+ * For reading and writing 8 and 16 bit quantities we need to
  * go through one of the three sparse address mapping regions
  * and use the HAE_MEM CSR to provide some bits of the address.
  * The following few routines use only sparse address region 1
@@ -410,10 +409,10 @@
  * See p 6-17 of the specification but it looks something like this:
  *
  * 21164 Address:
- * 
- *          3         2         1                                                               
+ *
+ *          3         2         1
  * 9876543210987654321098765432109876543210
- * 1ZZZZ0.PCI.QW.Address............BBLL                 
+ * 1ZZZZ0.PCI.QW.Address............BBLL
  *
  * ZZ = SBZ
  * BB = Byte offset
@@ -421,12 +420,12 @@
  *
  * PCI Address:
  *
- * 3         2         1                                                               
+ * 3         2         1
  * 10987654321098765432109876543210
  * HHH....PCI.QW.Address........ 00
  *
  * HHH = 31:29 HAE_MEM CSR
- * 
+ *
  */
 
 __EXTERN_INLINE unsigned long t2_srm_base(unsigned long addr)
@@ -495,19 +494,21 @@
 
 __EXTERN_INLINE void t2_srm_writeb(unsigned char b, unsigned long addr)
 {
-	unsigned long work = t2_srm_base(addr);
+	unsigned long w, work = t2_srm_base(addr);
 	if (work) {
 		work += 0x00;	/* add transfer length */
-		*(vuip) work = b * 0x01010101;
+		w = __kernel_insbl(b, addr & 3);
+		*(vuip) work = w;
 	}
 }
 
 __EXTERN_INLINE void t2_srm_writew(unsigned short b, unsigned long addr)
 {
-	unsigned long work = t2_srm_base(addr);
+	unsigned long w, work = t2_srm_base(addr);
 	if (work) {
 		work += 0x08;	/* add transfer length */
-		*(vuip) work = b * 0x00010001;
+		w = __kernel_inswl(b, addr & 3);
+		*(vuip) work = w;
 	}
 }
 
@@ -537,11 +538,11 @@
 {
 	unsigned long result, msb;
 
-	msb = addr & 0xE0000000 ;
-	addr &= T2_MEM_R1_MASK ;
+	msb = addr & 0xE0000000;
+	addr &= T2_MEM_R1_MASK;
 	set_hae(msb);
 
-	result = *(vip) ((addr << 5) + T2_SPARSE_MEM + 0x00) ;
+	result = *(vip) ((addr << 5) + T2_SPARSE_MEM + 0x00);
 	return __kernel_extbl(result, addr & 3);
 }
 
@@ -549,8 +550,8 @@
 {
 	unsigned long result, msb;
 
-	msb = addr & 0xE0000000 ;
-	addr &= T2_MEM_R1_MASK ;
+	msb = addr & 0xE0000000;
+	addr &= T2_MEM_R1_MASK;
 	set_hae(msb);
 
 	result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08);
@@ -562,8 +563,8 @@
 {
 	unsigned long msb;
 
-	msb = addr & 0xE0000000 ;
-	addr &= T2_MEM_R1_MASK ;
+	msb = addr & 0xE0000000;
+	addr &= T2_MEM_R1_MASK;
 	set_hae(msb);
 
 	return *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18);
@@ -573,8 +574,8 @@
 {
 	unsigned long r0, r1, work, msb;
 
-	msb = addr & 0xE0000000 ;
-	addr &= T2_MEM_R1_MASK ;
+	msb = addr & 0xE0000000;
+	addr &= T2_MEM_R1_MASK;
 	set_hae(msb);
 
 	work = (addr << 5) + T2_SPARSE_MEM + 0x18;
@@ -585,33 +586,35 @@
 
 __EXTERN_INLINE void t2_writeb(unsigned char b, unsigned long addr)
 {
-        unsigned long msb ; 
+	unsigned long msb, w;
 
-	msb = addr & 0xE0000000 ;
-	addr &= T2_MEM_R1_MASK ;
+	msb = addr & 0xE0000000;
+	addr &= T2_MEM_R1_MASK;
 	set_hae(msb);
 
-	*(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x00) = b * 0x01010101;
+	w = __kernel_insbl(b, addr & 3);
+	*(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x00) = w;
 }
 
 __EXTERN_INLINE void t2_writew(unsigned short b, unsigned long addr)
 {
-        unsigned long msb ; 
+	unsigned long msb, w;
 
-	msb = addr & 0xE0000000 ;
-	addr &= T2_MEM_R1_MASK ;
+	msb = addr & 0xE0000000;
+	addr &= T2_MEM_R1_MASK;
 	set_hae(msb);
 
-	*(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08) = b * 0x00010001;
+	w = __kernel_inswl(b, addr & 3);
+	*(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08) = w;
 }
 
 /* On SABLE with T2, we must use SPARSE memory even for 32-bit access. */
 __EXTERN_INLINE void t2_writel(unsigned int b, unsigned long addr)
 {
-        unsigned long msb ; 
+	unsigned long msb;
 
-	msb = addr & 0xE0000000 ;
-	addr &= T2_MEM_R1_MASK ;
+	msb = addr & 0xE0000000;
+	addr &= T2_MEM_R1_MASK;
 	set_hae(msb);
 
 	*(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18) = b;
@@ -619,10 +622,10 @@
 
 __EXTERN_INLINE void t2_writeq(unsigned long b, unsigned long addr)
 {
-        unsigned long msb, work;
+	unsigned long msb, work;
 
-	msb = addr & 0xE0000000 ;
-	addr &= T2_MEM_R1_MASK ;
+	msb = addr & 0xE0000000;
+	addr &= T2_MEM_R1_MASK;
 	set_hae(msb);
 
 	work = (addr << 5) + T2_SPARSE_MEM + 0x18;
@@ -630,11 +633,14 @@
 	*(vuip)(work + (4 << 5)) = b >> 32;
 }
 
-/* Find the DENSE memory area for a given bus address.  */
+__EXTERN_INLINE unsigned long t2_ioremap(unsigned long addr)
+{
+	return addr;
+}
 
-__EXTERN_INLINE unsigned long t2_dense_mem(unsigned long addr)
+__EXTERN_INLINE int t2_is_ioaddr(unsigned long addr)
 {
-	return T2_DENSE_MEM;
+	return (long)addr >= 0;
 }
 
 #undef vip
@@ -671,7 +677,8 @@
 #define __writeq	t2_writeq
 #endif
 
-#define dense_mem	t2_dense_mem
+#define __ioremap	t2_ioremap
+#define __is_ioaddr	t2_is_ioaddr
 
 #define inb(port) \
 (__builtin_constant_p((port))?__inb(port):_inb(port))