patch-2.3.16 linux/arch/alpha/kernel/core_apecs.c

• Lines: 292
• Date: Tue Aug 31 10:50:39 1999
• Orig file: v2.3.15/linux/arch/alpha/kernel/core_apecs.c
• Orig date: Fri Aug 13 11:53:50 1999

diff -u --recursive --new-file v2.3.15/linux/arch/alpha/kernel/core_apecs.c linux/arch/alpha/kernel/core_apecs.c
@@ -1,14 +1,15 @@
 /*
  *	linux/arch/alpha/kernel/core_apecs.c
  *
- * Code common to all APECS core logic chips.
- *
  * Rewritten for Apecs from the lca.c from:
  *
  * Written by David Mosberger (davidm@cs.arizona.edu) with some code
  * taken from Dave Rusling's (david.rusling@reo.mts.dec.com) 32-bit
  * bios code.
+ *
+ * Code common to all APECS core logic chips.
  */
+
 #include <linux/kernel.h>
 #include <linux/config.h>
 #include <linux/types.h>
@@ -18,6 +19,7 @@
 #include <asm/system.h>
 #include <asm/ptrace.h>
 #include <asm/smp.h>
+#include <asm/pci.h>
 
 #define __EXTERN_INLINE inline
 #include <asm/io.h>
@@ -25,6 +27,7 @@
 #undef __EXTERN_INLINE
 
 #include "proto.h"
+#include "pci_impl.h"
 
 /*
  * NOTE: Herein lie back-to-back mb instructions.  They are magic. 
@@ -89,10 +92,12 @@
  */
 
 static int
-mk_conf_addr(u8 bus, u8 device_fn, u8 where, unsigned long *pci_addr,
+mk_conf_addr(struct pci_dev *dev, int where, unsigned long *pci_addr,
 	     unsigned char *type1)
 {
 	unsigned long addr;
+	u8 bus = dev->bus->number;
+	u8 device_fn = dev->devfn;
 
 	DBGC(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x,"
 	      " pci_addr=0x%p, type1=0x%p)\n",
@@ -212,7 +217,6 @@
 
 	__save_and_cli(flags);	/* avoid getting hit by machine check */
 
-
 	/* Reset status register to avoid losing errors.  */
 	stat0 = *(vuip)APECS_IOC_DCSR;
 	*(vuip)APECS_IOC_DCSR = stat0;
@@ -270,162 +274,106 @@
 	__restore_flags(flags);
 }
 
-int
-apecs_hose_read_config_byte (u8 bus, u8 device_fn, u8 where, u8 *value,
-			     struct linux_hose_info *hose)
+static int
+apecs_read_config_byte(struct pci_dev *dev, int where, u8 *value)
 {
-	unsigned long addr = APECS_CONF;
-	unsigned long pci_addr;
+	unsigned long addr, pci_addr;
 	unsigned char type1;
 
-	if (mk_conf_addr(bus, device_fn, where, &pci_addr, &type1))
+	if (mk_conf_addr(dev, where, &pci_addr, &type1))
 		return PCIBIOS_DEVICE_NOT_FOUND;
 
-	addr |= (pci_addr << 5) + 0x00;
-
+	addr = (pci_addr << 5) + 0x00 + APECS_CONF;
 	*value = conf_read(addr, type1) >> ((where & 3) * 8);
-
 	return PCIBIOS_SUCCESSFUL;
 }
 
-int 
-apecs_hose_read_config_word (u8 bus, u8 device_fn, u8 where, u16 *value,
-			     struct linux_hose_info *hose)
+static int 
+apecs_read_config_word(struct pci_dev *dev, int where, u16 *value)
 {
-	unsigned long addr = APECS_CONF;
-	unsigned long pci_addr;
+	unsigned long addr, pci_addr;
 	unsigned char type1;
 
-	if (mk_conf_addr(bus, device_fn, where, &pci_addr, &type1))
+	if (mk_conf_addr(dev, where, &pci_addr, &type1))
 		return PCIBIOS_DEVICE_NOT_FOUND;
 
-	addr |= (pci_addr << 5) + 0x08;
-
+	addr = (pci_addr << 5) + 0x08 + APECS_CONF;
 	*value = conf_read(addr, type1) >> ((where & 3) * 8);
 	return PCIBIOS_SUCCESSFUL;
 }
 
-int
-apecs_hose_read_config_dword (u8 bus, u8 device_fn, u8 where, u32 *value,
-			      struct linux_hose_info *hose)
+static int
+apecs_read_config_dword(struct pci_dev *dev, int where, u32 *value)
 {
-	unsigned long addr = APECS_CONF;
-	unsigned long pci_addr;
+	unsigned long addr, pci_addr;
 	unsigned char type1;
 
-	if (mk_conf_addr(bus, device_fn, where, &pci_addr, &type1))
+	if (mk_conf_addr(dev, where, &pci_addr, &type1))
 		return PCIBIOS_DEVICE_NOT_FOUND;
 
-	addr |= (pci_addr << 5) + 0x18;
+	addr = (pci_addr << 5) + 0x18 + APECS_CONF;
 	*value = conf_read(addr, type1);
 	return PCIBIOS_SUCCESSFUL;
 }
 
-int
-apecs_hose_write_config_byte (u8 bus, u8 device_fn, u8 where, u8 value,
-			      struct linux_hose_info *hose)
+static int
+apecs_write_config(struct pci_dev *dev, int where, u32 value, long mask)
 {
-	unsigned long addr = APECS_CONF;
-	unsigned long pci_addr;
+	unsigned long addr, pci_addr;
 	unsigned char type1;
 
-	if (mk_conf_addr(bus, device_fn, where, &pci_addr, &type1))
+	if (mk_conf_addr(dev, where, &pci_addr, &type1))
 		return PCIBIOS_DEVICE_NOT_FOUND;
 
-	addr |= (pci_addr << 5) + 0x00;
+	addr = (pci_addr << 5) + mask + APECS_CONF;
 	conf_write(addr, value << ((where & 3) * 8), type1);
 	return PCIBIOS_SUCCESSFUL;
 }
 
-int 
-apecs_hose_write_config_word (u8 bus, u8 device_fn, u8 where, u16 value,
-			      struct linux_hose_info *hose)
+static int
+apecs_write_config_byte(struct pci_dev *dev, int where, u8 value)
 {
-	unsigned long addr = APECS_CONF;
-	unsigned long pci_addr;
-	unsigned char type1;
-
-	if (mk_conf_addr(bus, device_fn, where, &pci_addr, &type1))
-		return PCIBIOS_DEVICE_NOT_FOUND;
-
-	addr |= (pci_addr << 5) + 0x08;
-	conf_write(addr, value << ((where & 3) * 8), type1);
-	return PCIBIOS_SUCCESSFUL;
+	return apecs_write_config(dev, where, value, 0x00);
 }
 
-int 
-apecs_hose_write_config_dword (u8 bus, u8 device_fn, u8 where, u32 value,
-			       struct linux_hose_info *hose)
+static int
+apecs_write_config_word(struct pci_dev *dev, int where, u16 value)
 {
-	unsigned long addr = APECS_CONF;
-	unsigned long pci_addr;
-	unsigned char type1;
-
-	if (mk_conf_addr(bus, device_fn, where, &pci_addr, &type1))
-		return PCIBIOS_DEVICE_NOT_FOUND;
+	return apecs_write_config(dev, where, value, 0x08);
+}
 
-	addr |= (pci_addr << 5) + 0x18;
-	conf_write(addr, value << ((where & 3) * 8), type1);
-	return PCIBIOS_SUCCESSFUL;
+static int
+apecs_write_config_dword(struct pci_dev *dev, int where, u32 value)
+{
+	return apecs_write_config(dev, where, value, 0x18);
 }
 
+struct pci_ops apecs_pci_ops = 
+{
+	read_byte:	apecs_read_config_byte,
+	read_word:	apecs_read_config_word,
+	read_dword:	apecs_read_config_dword,
+	write_byte:	apecs_write_config_byte,
+	write_word:	apecs_write_config_word,
+	write_dword:	apecs_write_config_dword
+};
+
 void __init
 apecs_init_arch(unsigned long *mem_start, unsigned long *mem_end)
 {
-	switch (alpha_use_srm_setup)
-	{
-	default:
-#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SRM_SETUP)
-		/* Check window 1 for enabled and mapped to 0. */
-		if ((*(vuip)APECS_IOC_PB1R & (1U<<19))
-		    && (*(vuip)APECS_IOC_TB1R == 0)) {
-			APECS_DMA_WIN_BASE = *(vuip)APECS_IOC_PB1R & 0xfff00000U;
-			APECS_DMA_WIN_SIZE = *(vuip)APECS_IOC_PM1R & 0xfff00000U;
-			APECS_DMA_WIN_SIZE += 0x00100000U;
-#if 1
-			printk("apecs_init: using Window 1 settings\n");
-			printk("apecs_init: PB1R 0x%x PM1R 0x%x TB1R 0x%x\n",
-			       *(vuip)APECS_IOC_PB1R,
-			       *(vuip)APECS_IOC_PM1R,
-			       *(vuip)APECS_IOC_TB1R);
-#endif
-			break;
-		}
+	struct pci_controler *hose;
 
-		/* Check window 2 for enabled and mapped to 0.  */
-		if ((*(vuip)APECS_IOC_PB2R & (1U<<19))
-		    && (*(vuip)APECS_IOC_TB2R == 0)) {
-			APECS_DMA_WIN_BASE = *(vuip)APECS_IOC_PB2R & 0xfff00000U;
-			APECS_DMA_WIN_SIZE = *(vuip)APECS_IOC_PM2R & 0xfff00000U;
-			APECS_DMA_WIN_SIZE += 0x00100000U;
-#if 1
-			printk("apecs_init: using Window 2 settings\n");
-			printk("apecs_init: PB2R 0x%x PM2R 0x%x TB2R 0x%x\n",
-			       *(vuip)APECS_IOC_PB2R,
-			       *(vuip)APECS_IOC_PM2R,
-			       *(vuip)APECS_IOC_TB2R);
-#endif
-			break;
-		}
-		
-		/* Otherwise, we must use our defaults.  */
-		APECS_DMA_WIN_BASE = APECS_DMA_WIN_BASE_DEFAULT;
-		APECS_DMA_WIN_SIZE = APECS_DMA_WIN_SIZE_DEFAULT;
-#endif
-	case 0:
-		/*
-		 * Set up the PCI->physical memory translation windows.
-		 * For now, window 2 is disabled.  In the future, we may
-		 * want to use it to do scatter/gather DMA.  Window 1
-		 * goes at 1 GB and is 1 GB large.
-		 */
-		*(vuip)APECS_IOC_PB2R  = 0U; /* disable window 2 */
-
-		*(vuip)APECS_IOC_PB1R  = 1U<<19 | (APECS_DMA_WIN_BASE_DEFAULT & 0xfff00000U);
-		*(vuip)APECS_IOC_PM1R  = (APECS_DMA_WIN_SIZE_DEFAULT - 1) & 0xfff00000U;
-		*(vuip)APECS_IOC_TB1R  = 0;
-		break;
-	}
+	/*
+	 * Set up the PCI->physical memory translation windows.
+	 * For now, window 2 is disabled.  In the future, we may
+	 * want to use it to do scatter/gather DMA.  Window 1
+	 * goes at 1 GB and is 1 GB large.
+	 */
+	*(vuip)APECS_IOC_PB1R = 1UL << 19 | (APECS_DMA_WIN_BASE & 0xfff00000U);
+	*(vuip)APECS_IOC_PM1R = (APECS_DMA_WIN_SIZE - 1) & 0xfff00000U;
+	*(vuip)APECS_IOC_TB1R = 0;
+
+	*(vuip)APECS_IOC_PB2R = 0U;	/* disable window 2 */
 
 	/*
 	 * Finally, clear the HAXR2 register, which gets used
@@ -433,7 +381,18 @@
 	 * we want to use it, and we do not want to depend on
 	 * what ARC or SRM might have left behind...
 	 */
-	*(vuip)APECS_IOC_HAXR2 = 0; mb();
+	*(vuip)APECS_IOC_HAXR2 = 0;
+	mb();
+
+	/*
+	 * Create our single hose.
+	 */
+
+	hose = alloc_pci_controler(mem_start);
+	hose->io_space = &ioport_resource;
+	hose->mem_space = &iomem_resource;
+	hose->config_space = APECS_CONF;
+	hose->index = 0;
 }
 
 void