patch-2.3.48 linux/arch/mips/kernel/r4k_switch.S

• Lines: 169
• Date: Thu Feb 24 22:52:30 2000
• Orig file: v2.3.47/linux/arch/mips/kernel/r4k_switch.S
• Orig date: Fri Jun 25 17:40:12 1999

diff -u --recursive --new-file v2.3.47/linux/arch/mips/kernel/r4k_switch.S linux/arch/mips/kernel/r4k_switch.S
@@ -1,4 +1,4 @@
-/* $Id: r4k_switch.S,v 1.7 1999/06/13 16:30:32 ralf Exp $
+/* $Id: r4k_switch.S,v 1.10 1999/10/09 00:00:58 ralf Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -7,13 +7,13 @@
  * Copyright (C) 1994, 1995, 1996, 1998, 1999 by Ralf Baechle
  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
  * Copyright (C) 1994, 1995, 1996, by Andreas Busse
+ * Copyright (C) 1999 Silicon Graphics, Inc.
  */
 #include <asm/asm.h>
 #include <asm/bootinfo.h>
 #include <asm/cachectl.h>
 #include <asm/current.h>
 #include <asm/fpregdef.h>
-#include <asm/mipsconfig.h>
 #include <asm/mipsregs.h>
 #include <asm/offset.h>
 #include <asm/page.h>
@@ -24,14 +24,14 @@
 
 #include <asm/asmmacro.h>
 
+	.set	mips3
+
 /*
- * task_struct *r4xx0_resume(task_struct *prev,
- *                           task_struct *next)
+ * task_struct *r4xx0_resume(task_struct *prev, task_struct *next)
  */
 	.set	noreorder
-	.set	mips3
 	.align	5
-	LEAF(r4xx0_resume)
+	LEAF(resume)
 	mfc0	t1, CP0_STATUS
 	sw	t1, THREAD_STATUS(a0)
 	CPU_SAVE_NONSCRATCH(a0)
@@ -51,15 +51,11 @@
 	lw	a2, THREAD_STATUS($28)
 	nor	a3, $0, a3
 	and	a2, a3
-	lw	a3, TASK_MM($28)
 	or	a2, t1
-	lw	a3, MM_CONTEXT(a3)
 	mtc0	a2, CP0_STATUS
-	andi	a3, a3, 0xff
-	mtc0	a3, CP0_ENTRYHI
 	jr	ra
 	 move	v0, a0
-	END(r4xx0_resume)
+	END(resume)
 
 /*
  * Do lazy fpu context switch.  Saves FPU context to the process in a0
@@ -68,7 +64,7 @@
 
 #define ST_OFF (KERNEL_STACK_SIZE - 32 - PT_SIZE + PT_STATUS)
 
-LEAF(r4xx0_lazy_fpu_switch)
+LEAF(lazy_fpu_switch)
 	mfc0	t0, CP0_STATUS			# enable cp1
 	li	t3, 0x20000000
 	or	t0, t3
@@ -76,42 +72,27 @@
 
 	beqz	a0, 2f				# Save floating point state
 	 nor	t3, zero, t3
+
 	lw	t1, ST_OFF(a0)			# last thread looses fpu
 	and	t1, t3
 	sw	t1, ST_OFF(a0)
-	sll	t2, t1, 5
-	bgez	t2, 1f
-	 sdc1	$f0, (THREAD_FPU + 0x00)(a0)
-	FPU_SAVE_16ODD(a0)
-1:
-	FPU_SAVE_16EVEN(a0, t1)			# clobbers t1
+
+
+	FPU_SAVE_DOUBLE(a0, t1)			# clobbers t1
 2:
 
-	sll	t0, t0, 5			# load new fp state
-	bgez	t0, 1f
-	 ldc1	$f0, (THREAD_FPU + 0x00)($28)
-	FPU_RESTORE_16ODD($28)
-1:
 	.set	reorder
-	FPU_RESTORE_16EVEN($28, t0)		# clobbers t0
+	FPU_RESTORE_DOUBLE($28, t0)		# clobbers t0
 	jr	ra
-	END(r4xx0_lazy_fpu_switch)
+	END(lazy_fpu_switch)
 
 /*
  * Save a thread's fp context.
  */
-	.set	noreorder
-LEAF(r4xx0_save_fp)
-	mfc0	t0, CP0_STATUS
-	sll	t1, t0, 5
-	bgez	t1, 1f				# 16 register mode?
-	 nop
-	FPU_SAVE_16ODD(a0)
-1:
-	FPU_SAVE_16EVEN(a0, t1)			# clobbers t1
+LEAF(save_fp)
+	FPU_SAVE_DOUBLE(a0, t1)			# clobbers t1
 	jr	ra
-	 sdc1	$f0, (THREAD_FPU + 0x00)(a0)
-	END(r4xx0_save_fp)
+	END(save_fp)
 
 /*
  * Load the FPU with signalling NANS.  This bit pattern we're using has
@@ -123,37 +104,18 @@
 
 #define FPU_DEFAULT  0x00000000
 
-LEAF(r4xx0_init_fpu)
+LEAF(init_fpu)
 	mfc0	t0, CP0_STATUS
 	li	t1, 0x20000000
 	or	t0, t1
 	mtc0	t0, CP0_STATUS
-	sll	t0, t0, 5
 
 	li	t1, FPU_DEFAULT
 	ctc1	t1, fcr31
 
-	bgez	t0, 1f			# 16 / 32 register mode?
-	 li	t0, -1
-
-	dmtc1	t0, $f1
-	dmtc1	t0, $f3
-	dmtc1	t0, $f5
-	dmtc1	t0, $f7
-	dmtc1	t0, $f9
-	dmtc1	t0, $f11
-	dmtc1	t0, $f13
-	dmtc1	t0, $f15
-	dmtc1	t0, $f17
-	dmtc1	t0, $f19
-	dmtc1	t0, $f21
-	dmtc1	t0, $f23
-	dmtc1	t0, $f25
-	dmtc1	t0, $f27
-	dmtc1	t0, $f29
-	dmtc1	t0, $f31
+	li	t0, -1
 
-1:	dmtc1	t0, $f0
+	dmtc1	t0, $f0
 	dmtc1	t0, $f2
 	dmtc1	t0, $f4
 	dmtc1	t0, $f6
@@ -168,6 +130,8 @@
 	dmtc1	t0, $f24
 	dmtc1	t0, $f26
 	dmtc1	t0, $f28
+	.set	noreorder
 	jr	ra
 	 dmtc1	t0, $f30
-	END(r4xx0_init_fpu)
+	.set	reorder
+	END(init_fpu)