patch-2.3.49 linux/arch/alpha/kernel/sys_sable.c

• Lines: 76
• Date: Mon Feb 28 14:54:30 2000
• Orig file: v2.3.48/linux/arch/alpha/kernel/sys_sable.c
• Orig date: Sun Feb 20 21:12:38 2000

diff -u --recursive --new-file v2.3.48/linux/arch/alpha/kernel/sys_sable.c linux/arch/alpha/kernel/sys_sable.c
@@ -30,6 +30,7 @@
 #include "pci_impl.h"
 #include "machvec_impl.h"
 
+spinlock_t sable_irq_lock = SPIN_LOCK_UNLOCKED;
 
 /*
  *   For SABLE, which is really baroque, we manage 40 IRQ's, but the
@@ -137,8 +138,10 @@
 	unsigned long bit, mask;
 
 	bit = sable_irq_swizzle.irq_to_mask[irq];
+	spin_lock(&sable_irq_lock);
 	mask = sable_irq_swizzle.shadow_mask &= ~(1UL << bit);
 	sable_update_irq_hw(bit, mask);
+	spin_unlock(&sable_irq_lock);
 }
 
 static void
@@ -147,8 +150,10 @@
 	unsigned long bit, mask;
 
 	bit = sable_irq_swizzle.irq_to_mask[irq];
+	spin_lock(&sable_irq_lock);
 	mask = sable_irq_swizzle.shadow_mask |= 1UL << bit;
 	sable_update_irq_hw(bit, mask);
+	spin_unlock(&sable_irq_lock);
 }
 
 static unsigned int
@@ -159,14 +164,23 @@
 }
 
 static void
+sable_end_irq(unsigned int irq)
+{
+	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
+		sable_enable_irq(irq);
+}
+
+static void
 sable_mask_and_ack_irq(unsigned int irq)
 {
 	unsigned long bit, mask;
 
 	bit = sable_irq_swizzle.irq_to_mask[irq];
+	spin_lock(&sable_irq_lock);
 	mask = sable_irq_swizzle.shadow_mask |= 1UL << bit;
 	sable_update_irq_hw(bit, mask);
 	sable_ack_irq_hw(bit);
+	spin_unlock(&sable_irq_lock);
 }
 
 static struct hw_interrupt_type sable_irq_type = {
@@ -176,7 +190,7 @@
 	enable:		sable_enable_irq,
 	disable:	sable_disable_irq,
 	ack:		sable_mask_and_ack_irq,
-	end:		sable_enable_irq,
+	end:		sable_end_irq,
 };
 
 static void 
@@ -204,11 +218,10 @@
 	outb(0x44, 0x535);	/* enable cascades in master */
 
 	for (i = 0; i < 40; ++i) {
-		irq_desc[i].status = IRQ_DISABLED;
+		irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
 		irq_desc[i].handler = &sable_irq_type;
 	}
 	
-	init_rtc_irq();
 	common_init_isa_dma();
 }