patch-2.3.7 linux/arch/arm/kernel/dec21285.c

• Lines: 139
• Date: Thu Jun 17 01:11:35 1999
• Orig file: v2.3.6/linux/arch/arm/kernel/dec21285.c
• Orig date: Thu Dec 17 09:05:42 1998

diff -u --recursive --new-file v2.3.6/linux/arch/arm/kernel/dec21285.c linux/arch/arm/kernel/dec21285.c
@@ -8,17 +8,17 @@
 #include <linux/pci.h>
 #include <linux/ptrace.h>
 #include <linux/interrupt.h>
+#include <linux/mm.h>
 #include <linux/init.h>
 
 #include <asm/irq.h>
 #include <asm/system.h>
+#include <asm/hardware.h>
 
-#define MAX_SLOTS		20
+#define MAX_SLOTS		21
 
 extern void pcibios_fixup_ebsa285(struct pci_dev *dev);
 extern void pcibios_init_ebsa285(void);
-extern void pcibios_fixup_vnc(struct pci_dev *dev);
-extern void pcibios_init_vnc(void);
 
 int
 pcibios_present(void)
@@ -33,11 +33,12 @@
 		int slot = PCI_SLOT(dev_fn);
 		
 		if (slot < MAX_SLOTS)
-			return 0xf8c00000 + (slot << 11) + (PCI_FUNC(dev_fn) << 8);
+			return PCICFG0_BASE + 0xc00000 +
+				(slot << 11) + (PCI_FUNC(dev_fn) << 8);
 		else
 			return 0;
 	} else
-		return 0xf9000000 | (bus << 16) | (dev_fn << 8);
+		return PCICFG1_BASE | (bus << 16) | (dev_fn << 8);
 }
 
 int
@@ -151,10 +152,7 @@
 	struct pci_dev *dev;
 
 	for (dev = pci_devices; dev; dev = dev->next) {
-		if (machine_is_ebsa285() || machine_is_cats())
-			pcibios_fixup_ebsa285(dev);
-		if (machine_is_netwinder())
-			pcibios_fixup_vnc(dev);
+		pcibios_fixup_ebsa285(dev);
 
 		pcibios_write_config_byte(dev->bus->number, dev->devfn,
 					  PCI_INTERRUPT_LINE, dev->irq);
@@ -164,18 +162,83 @@
 			dev->bus->number, dev->devfn,
 			dev->vendor, dev->device, dev->irq);
 	}
-	if (machine_is_netwinder())
-		hw_init();
+
+	hw_init();
 }
 
 __initfunc(void pcibios_init(void))
 {
-	if (machine_is_ebsa285() || machine_is_cats())
-		pcibios_init_ebsa285();
-	if (machine_is_netwinder())
-		pcibios_init_vnc();
+	unsigned int mem_size = (unsigned int)high_memory - PAGE_OFFSET;
+	unsigned long cntl;
+
+	*CSR_SDRAMBASEMASK    = (mem_size - 1) & 0x0ffc0000;
+	*CSR_SDRAMBASEOFFSET  = 0;
+	*CSR_ROMBASEMASK      = 0x80000000;
+	*CSR_CSRBASEMASK      = 0;
+	*CSR_CSRBASEOFFSET    = 0;
+	*CSR_PCIADDR_EXTN     = 0;
+
+#ifdef CONFIG_HOST_FOOTBRIDGE
+	/*
+	 * Against my better judgement, Philip Blundell still seems
+	 * to be saying that we should initialise the PCI stuff here
+	 * when the PCI_CFN bit is not set, dispite my comment below,
+	 * which he decided to remove.  If it is not set, then
+	 * the card is in add-in mode, and we're in a machine where
+	 * the bus is set up by 'others'.
+	 *
+	 * We should therefore not mess about with the mapping in
+	 * anyway, and we should not be using the virt_to_bus functions
+	 * that exist in the HOST architecture mode (since they assume
+	 * a fixed mapping).
+	 *
+	 * Instead, you should be using ADDIN mode, which allows for
+	 * this situation.  This does assume that you have correctly
+	 * initialised the PCI bus, which you must have done to get
+	 * your PC booted.
+	 *
+	 * Unfortunately, he seems to be blind to this.  I guess he'll
+	 * also remove all this.
+	 *
+	 * And THIS COMMENT STAYS, even if this gets patched, thank
+	 * you.
+	 */
+
+	/*
+	 * Map our SDRAM at a known address in PCI space, just in case
+	 * the firmware had other ideas.  Using a nonzero base is
+	 * necessary, since some VGA cards forcefully use PCI addresses
+	 * in the range 0x000a0000 to 0x000c0000. (eg, S3 cards).
+	 *
+	 * NOTE! If you need to chec the PCI_CFN bit in the SA110
+	 * control register then you've configured the kernel wrong.
+	 * If you're not using host mode, then DO NOT set
+	 * CONFIG_HOST_FOOTBRIDGE, but use CONFIG_ADDIN_FOOTBRIDGE
+	 * instead.  In this case, you MUST supply some firmware
+	 * to allow your PC to boot, plus we should not modify the
+	 * mappings that the PC BIOS has set up for us.
+	 */
+	*CSR_PCICACHELINESIZE = 0x00002008;
+	*CSR_PCICSRBASE       = 0;
+	*CSR_PCICSRIOBASE     = 0;
+	*CSR_PCISDRAMBASE     = virt_to_bus((void *)PAGE_OFFSET);
+	*CSR_PCIROMBASE       = 0;
+	*CSR_PCICMD           = PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
+				PCI_COMMAND_MASTER | PCI_COMMAND_FAST_BACK |
+				PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY |
+				(1 << 31) | (1 << 29) | (1 << 28) | (1 << 24);
+#endif
+
+	/*
+	 * Clear any existing errors - we aren't
+	 * interested in historical data...
+	 */
+	cntl = *CSR_SA110_CNTL & 0xffffde07;
+	*CSR_SA110_CNTL = cntl | SA110_CNTL_RXSERR;
+
+	pcibios_init_ebsa285();
 
-	printk("DEC21285 PCI revision %02X\n", *(unsigned char *)0xfe000008);
+	printk(KERN_DEBUG"PCI: DEC21285 revision %02lX\n", *CSR_CLASSREV & 0xff);
 }
 
 __initfunc(void pcibios_fixup_bus(struct pci_bus *bus))