patch-2.3.99-pre6 linux/drivers/i2o/i2o_pci.c

• Lines: 48
• Date: Wed Apr 12 09:38:53 2000
• Orig file: v2.3.99-pre5/linux/drivers/i2o/i2o_pci.c
• Orig date: Thu Jan 6 12:57:47 2000

diff -u --recursive --new-file v2.3.99-pre5/linux/drivers/i2o/i2o_pci.c linux/drivers/i2o/i2o_pci.c
@@ -53,8 +53,10 @@
 	iounmap(((u8 *)c->post_port)-0x40);
 
 #ifdef CONFIG_MTRR
-	if(c->bus.pci.mtrr_reg > 0)
-		mtrr_del(c->bus.pci.mtrr_reg, 0, 0);
+       if(c->bus.pci.mtrr_reg0 > 0)
+               mtrr_del(c->bus.pci.mtrr_reg0, 0, 0);
+       if(c->bus.pci.mtrr_reg1 > 0)
+               mtrr_del(c->bus.pci.mtrr_reg1, 0, 0);
 #endif
 }
 
@@ -176,8 +178,22 @@
 	 * Enable Write Combining MTRR for IOP's memory region
 	 */
 #ifdef CONFIG_MTRR
-	c->bus.pci.mtrr_reg = 
-		mtrr_add(c->mem_phys, size, MTRR_TYPE_WRCOMB, 1);
+       c->bus.pci.mtrr_reg0 =
+                mtrr_add(c->mem_phys, size, MTRR_TYPE_WRCOMB, 1);
+/*
+* If it is an INTEL i960 I/O processor then set the first 64K to Uncacheable
+* since the region contains the Messaging unit which shouldn't be cached.
+*/
+       c->bus.pci.mtrr_reg1 = -1;
+       if(dev->vendor == PCI_VENDOR_ID_INTEL)
+        {
+       printk(KERN_INFO "i2o_pci: MTRR workaround for Intel i960 processor\n"); 
+       c->bus.pci.mtrr_reg1 =
+                mtrr_add(c->mem_phys, 65536, MTRR_TYPE_UNCACHABLE, 1);
+        if(c->bus.pci.mtrr_reg1< 0)
+                        printk(KERN_INFO "i2o_pci: Error in setting MTRR_TYPE_UNCACHABLE\n");
+       }
+
 #endif
 
 	I2O_IRQ_WRITE32(c,0xFFFFFFFF);
@@ -230,7 +246,8 @@
 	
 	printk(KERN_INFO "i2o: Checking for PCI I2O controllers...\n");
 
-	pci_for_each_dev(dev) {
+	pci_for_each_dev(dev)	
+	{
 		if((dev->class>>8)!=PCI_CLASS_INTELLIGENT_I2O)
 			continue;
 		if((dev->class&0xFF)>1)