patch-2.3.99-pre9 linux/arch/mips64/sgi-ip27/ip27-pci.c

• Lines: 242
• Date: Sat May 13 08:30:17 2000
• Orig file: v2.3.99-pre8/linux/arch/mips64/sgi-ip27/ip27-pci.c
• Orig date: Sat Feb 26 22:31:41 2000

diff -u --recursive --new-file v2.3.99-pre8/linux/arch/mips64/sgi-ip27/ip27-pci.c linux/arch/mips64/sgi-ip27/ip27-pci.c
@@ -13,6 +13,8 @@
 #include <asm/sn/arch.h>
 #include <asm/pci/bridge.h>
 #include <asm/paccess.h>
+#include <asm/sn/sn0/ip27.h>
+#include <asm/sn/sn0/hub.h>
 
 /*
  * The Bridge ASIC supports both type 0 and type 1 access.  Type 1 is
@@ -22,14 +24,18 @@
  */
 #define CF0_READ_PCI_CFG(dev,where,value,bm,mask)			\
 do {									\
-	bridge_t *bridge = (bridge_t *) 0x9200000008000000;		\
+	bridge_t *bridge;                                               \
 	int slot = PCI_SLOT(dev->devfn);				\
 	int fn = PCI_FUNC(dev->devfn);					\
 	volatile u32 *addr;						\
 	u32 cf, __bit;							\
+	unsigned int bus_id = (unsigned) dev->bus->number;              \
 									\
-	if (dev->bus->number)						\
-		return PCIBIOS_DEVICE_NOT_FOUND;			\
+	bridge = (bridge_t *) NODE_SWIN_BASE(bus_to_nid[bus_id],        \
+                                             bus_to_wid[bus_id]);       \
+                                                                        \
+	/*if (dev->bus->number)			 */			\
+	/*	return PCIBIOS_DEVICE_NOT_FOUND; */			\
 									\
 	__bit = (((where) & (bm)) << 3);				\
 	addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];	\
@@ -59,14 +65,18 @@
 
 #define CF0_WRITE_PCI_CFG(dev,where,value,bm,mask)			\
 do {									\
-	bridge_t *bridge = (bridge_t *) 0x9200000008000000;		\
+	bridge_t *bridge;                                               \
 	int slot = PCI_SLOT(dev->devfn);				\
 	int fn = PCI_FUNC(dev->devfn);					\
 	volatile u32 *addr;						\
 	u32 cf, __bit;							\
+	unsigned int bus_id = (unsigned) dev->bus->number;              \
 									\
-	if (dev->bus->number)						\
-		return PCIBIOS_DEVICE_NOT_FOUND;			\
+	bridge = (bridge_t *) NODE_SWIN_BASE(bus_to_nid[bus_id],        \
+                                             bus_to_wid[bus_id]);       \
+                                                                        \
+	/* if (dev->bus->number)		 */			\
+	/* 	return PCIBIOS_DEVICE_NOT_FOUND; */			\
 									\
 	if (dev->vendor == PCI_VENDOR_ID_SGI				\
 	    && dev->device == PCI_DEVICE_ID_SGI_IOC3)			\
@@ -114,11 +124,14 @@
 {
 	struct pci_ops *ops = &bridge_pci_ops;
 	nasid_t nid = get_nasid();
+	int	i;
 
 	ioport_resource.end = ~0UL;
 
-	printk("PCI: Probing PCI hardware on host bus 0, node %d.\n", nid);
-	pci_scan_bus(0, ops, NULL);
+	for (i=0; i<num_bridges; i++) {
+		printk("PCI: Probing PCI hardware on host bus %2d, node %d.\n", i, nid);
+		pci_scan_bus(i, ops, NULL);
+	}
 }
 
 static inline u8
@@ -145,7 +158,11 @@
 static int __init
 pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 {
-	return (slot + (((pin-1) & 1) << 2)) & 7;
+	int rv;
+	rv = (slot + (((pin-1) & 1) << 2)) & 7;
+	rv |= (bus_to_wid[dev->bus->number] << 8);
+	rv |= (bus_to_nid[dev->bus->number] << 16);
+	return rv;
 }
 
 void __init
@@ -171,33 +188,7 @@
 void __init
 pcibios_fixup_bus(struct pci_bus *b)
 {
-	unsigned short command;
-	struct list_head *ln;
-	struct pci_dev *dev;
-
 	pci_fixup_irqs(pci_swizzle, pci_map_irq);
-
-	/*
-	 * Older qlogicisp driver expects to have the IO space enable 
-	 * bit set. Make that happen for qlogic in slots 0 and 1. Things
-	 * stop working if we program the controllers as not having
-	 * PCI_COMMAND_MEMORY, so we have to fudge the mem_flags.
-	 */
-	for (ln=b->devices.next; ln != &b->devices; ln=ln->next) {
-		dev = pci_dev_b(ln);
-		if (PCI_FUNC(dev->devfn) == 0) {
-			if ((PCI_SLOT(dev->devfn) == 0) || 
-						(PCI_SLOT(dev->devfn) == 1)) {
-				if (pci_read_config_word(dev, PCI_COMMAND, 
-								&command) == 0) {
-					command |= PCI_COMMAND_IO;
-					pci_write_config_word(dev, PCI_COMMAND, 
-									command);
-					dev->resource[1].flags |= 1;
-				}
-			}
-		}
-	}
 }
 
 void __init
@@ -239,7 +230,7 @@
 	   with tons of bogus information in the pci_dev.  On Origins the
 	   INTA, INTB and INTC pins are all wired together as if it'd only
 	   use INTA.  */
-	printk("PCI: Fixing base addresses for device %s\n", d->slot_name);
+	printk("PCI: Fixing base addresses for IOC3 device %s\n", d->slot_name);
 
 	for (i = 1; i <= PCI_ROM_RESOURCE; i++) {
 		d->resource[i].start = 0UL;
@@ -251,8 +242,115 @@
 	d->irq = 1;
 }
 
+static void __init
+pci_fixup_isp1020(struct pci_dev *d)
+{
+	unsigned short command;
+
+	printk("PCI: Fixing isp1020 in [bus:slot.fn] %s\n", d->slot_name);
+
+	/* Configure device to allow bus mastering, i/o and memory mapping. 
+	 * Older qlogicisp driver expects to have the IO space enable 
+	 * bit set. Things stop working if we program the controllers as not having
+	 * PCI_COMMAND_MEMORY, so we have to fudge the mem_flags.
+	 */
+
+	/* only turn on scsi's on main bus */
+	if (d->bus->number == 0) {
+		pci_set_master(d);
+		pci_read_config_word(d, PCI_COMMAND, &command);
+		command |= PCI_COMMAND_MEMORY;
+		command |= PCI_COMMAND_IO;
+		pci_write_config_word(d, PCI_COMMAND, command);
+		d->resource[1].flags |= 1;
+	}
+}
+static void __init
+pci_fixup_isp2x00(struct pci_dev *d)
+{
+	unsigned int bus_id = (unsigned) d->bus->number;
+	bridge_t *bridge = (bridge_t *) NODE_SWIN_BASE(bus_to_nid[bus_id],
+				     bus_to_wid[bus_id]);
+	bridgereg_t 	devreg;
+	int		i;
+	int		slot = PCI_SLOT(d->devfn);
+	unsigned int	start;
+	unsigned short command;
+
+	printk("PCI: Fixing isp2x00 in [bus:slot.fn] %s\n", d->slot_name);
+
+	/* set the resource struct for this device */
+	start = (u32) bridge;	/* yes, we want to lose the upper 32 bits here */
+	start |= BRIDGE_DEVIO(slot);
+
+	d->resource[0].start = start;
+	d->resource[0].end = d->resource[0].start + 0xff;
+	d->resource[0].flags = IORESOURCE_IO;
+
+	d->resource[1].start = start;
+	d->resource[1].end = d->resource[0].start + 0xfff;
+	d->resource[1].flags = IORESOURCE_MEM;
+
+	/*
+	 * set the bridge device(x) reg for this device
+	 */
+	devreg = bridge->b_device[slot].reg;
+	/* point device(x) to it appropriate small window */
+	devreg &= ~BRIDGE_DEV_OFF_MASK;
+	devreg |= (start >> 20) & BRIDGE_DEV_OFF_MASK;
+
+	/* turn on byte swapping in direct map mode (how we currently run dma's) */
+	devreg |= BRIDGE_DEV_SWAP_DIR;		/* turn on byte swapping */
+
+	bridge->b_device[slot].reg = devreg;
+
+	/* set card's base addr reg */
+	//pci_conf0_write_config_dword(d, PCI_BASE_ADDRESS_0, 0x500001);
+	//pci_conf0_write_config_dword(d, PCI_BASE_ADDRESS_1, 0x8b00000);
+	//pci_conf0_write_config_dword(d, PCI_ROM_ADDRESS, 0x8b20000);
+
+	/* I got these from booting irix on system...*/
+	pci_conf0_write_config_dword(d, PCI_BASE_ADDRESS_0, 0x200001);
+	//pci_conf0_write_config_dword(d, PCI_BASE_ADDRESS_1, 0xf800000);
+	pci_conf0_write_config_dword(d, PCI_ROM_ADDRESS,   0x10200000);
+
+	pci_conf0_write_config_dword(d, PCI_BASE_ADDRESS_1, start);
+	//pci_conf0_write_config_dword(d, PCI_ROM_ADDRESS, (start | 0x20000));
+
+
+	/* set cache line size */
+	pci_conf0_write_config_dword(d, PCI_CACHE_LINE_SIZE, 0xf080);
+
+	/* set pci bus timeout */
+	bridge->b_bus_timeout |= BRIDGE_BUS_PCI_RETRY_HLD(0x3);
+	bridge->b_wid_tflush;
+	printk("PCI: bridge bus timeout= 0x%x \n", bridge->b_bus_timeout);
+
+	/* set host error field */
+	bridge->b_int_host_err = 0x44;
+	bridge->b_wid_tflush;
+		
+	bridge->b_wid_tflush;   	/* wait until Bridge PIO complete */
+	for (i=0; i<8; i++)
+		printk("PCI: device(%d)= 0x%x\n",i,bridge->b_device[i].reg);
+
+	/* configure device to allow bus mastering, i/o and memory mapping */
+	pci_set_master(d);
+	pci_read_config_word(d, PCI_COMMAND, &command);
+	command |= PCI_COMMAND_MEMORY;
+	command |= PCI_COMMAND_IO;
+	pci_write_config_word(d, PCI_COMMAND, command);
+	/*d->resource[1].flags |= 1;*/
+}
+
 struct pci_fixup pcibios_fixups[] = {
 	{ PCI_FIXUP_HEADER, PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
 	  pci_fixup_ioc3 },
+	{ PCI_FIXUP_HEADER, PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP1020,
+	  pci_fixup_isp1020 },
+	{ PCI_FIXUP_HEADER, PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100,
+	  pci_fixup_isp2x00 },
+	{ PCI_FIXUP_HEADER, PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200,
+	  pci_fixup_isp2x00 },
 	{ 0 }
 };