patch-2.4.10 linux/arch/mips/sni/int-handler.S

• Lines: 115
• Date: Sun Sep 9 10:43:02 2001
• Orig file: v2.4.9/linux/arch/mips/sni/int-handler.S
• Orig date: Sat May 13 08:29:14 2000

diff -u --recursive --new-file v2.4.9/linux/arch/mips/sni/int-handler.S linux/arch/mips/sni/int-handler.S
@@ -1,8 +1,7 @@
-/* $Id: int-handler.S,v 1.4 1999/01/04 16:03:58 ralf Exp $
- *
+/*
  * SNI RM200 PCI specific interrupt handler code.
  *
- * Copyright (C) 1994 - 1997 by Ralf Baechle
+ * Copyright (C) 1994, 95, 96, 97, 98, 1999, 2000 by Ralf Baechle
  */
 #include <asm/asm.h>
 #include <asm/mipsregs.h>
@@ -37,22 +36,14 @@
 		mfc0	t1, CP0_CAUSE
 		and	t0, t1
 
-		/* The following interrupt dispatch tests for hwint 1 /
-		   EISA bridge first such that the timer interrupt get the
-		   highest priority.  */
-		 andi	t1, t0, 0x0800			# hardware interrupt 1
-		bnez	t1, hwint1
-		 andi	t1, t0, 0x4000			# hardware interrupt 4
-		bnez	t1, hwint4
-
+		 andi	t1, t0, 0x4a00			# hardware interrupt 1
+		bnez	t1, _hwint134
 		 andi	t1, t0, 0x1000			# hardware interrupt 2
-		bnez	t1, hwint2
-		 andi	t1, t0, 0x2000			# hardware interrupt 3
-		bnez	t1, hwint3
+		bnez	t1, _hwint2
 		 andi	t1, t0, 0x8000			# hardware interrupt 5
-		bnez	t1, hwint5
+		bnez	t1, _hwint5
 		 andi	t1, t0, 0x0400			# hardware interrupt 0
-		bnez	t1, hwint0
+		bnez	t1, _hwint0
 		 nop
 
 		j	return				# spurious interrupt
@@ -60,66 +51,23 @@
 
  ##############################################################################
 
-swint0:		PANIC("swint0")
-swint1:		PANIC("swint1")
-
- /* ------------------------------------------------------------------------ */
-
-/* hwint1 deals with EISA and SCSI interrupts.  */
-hwint1:		lbu	s0, PCIMT_CSITPEND
-
-		andi	t1, s0, 0x20
-		beqz	t1, 1f
-		 andi	s1, s0, 0x40
-		lbu	a0, PCIMT_INT_ACKNOWLEDGE	# IACK cycle
-		xori	t0, a0, 0xff
-		beqz	t0, 1f				# spurious interrupt?
-		 nop
-		jal	i8259_do_irq			# call real handler
-		 move	a1, sp
-
-1:		bnez	s1, 1f
-		 li	a0, PCIMT_IRQ_SCSI
-		jal	do_IRQ
-		 move	a1, sp
-
-1:		lui	t0, %hi(PCIMT_CSITPEND)
-		j	ret_from_irq
-		 lbu	zero, %lo(PCIMT_CSITPEND)(t0)
-
- /* ------------------------------------------------------------------------ */
-
 /* hwint0 should deal with MP agent, ASIC PCI, EISA NMI and debug
    button interrupts.  */
-hwint0:		PANIC("Received int0 but no handler yet ...\n")
-1:		j	1b
-		 nop
-
-go_spurious:	j	spurious_interrupt		# we got fooled
-		 nop
-
-/* hwint4 is used for only the onboard PCnet 32.  */
-hwint4:		mfc0	s0, CP0_STATUS
-		ori	t0, s0, 0x4000
-		xori	t0, 0x4000
-		mtc0	t0, CP0_STATUS
-
-		li	a0, PCIMT_IRQ_ETHERNET
-		jal	do_IRQ
+_hwint0:	jal	pciasic_hwint0
 		 move	a1, sp
 
-		mtc0	s0, CP0_STATUS
+/*
+ * hwint 1 deals with EISA and SCSI interrupts,
+ * hwint 3 should deal with the PCI A - D interrupts,
+ * hwint 4 is used for only the onboard PCnet 32.
+ */
+_hwint134:	jal	pciasic_hwint134
 
-		j	ret_from_irq
-		 nop
 
 /* This interrupt was used for the com1 console on the first prototypes.  */
-hwint2:		PANIC("hwint2 and no handler yet")
-
-/* hwint3 should deal with the PCI A - D interrupts.  */
-hwint3:		PANIC("hwint3 and no handler yet")
+_hwint2:	jal	pciasic_hwint2
 
 /* hwint5 is the r4k count / compare interrupt  */
-hwint5:		PANIC("hwint5 and no handler yet")
+_hwint5:	jal	pciasic_hwint5
 
 		END(sni_rm200_pci_handle_int)