patch-2.4.11-dontuse linux/arch/cris/lib/dram_init.S

• Lines: 182
• Date: Mon Oct 8 11:43:54 2001
• Orig file: v2.4.10/linux/arch/cris/lib/dram_init.S
• Orig date: Wed Jul 25 17:10:17 2001

diff -u --recursive --new-file v2.4.10/linux/arch/cris/lib/dram_init.S linux/arch/cris/lib/dram_init.S
@@ -1,4 +1,4 @@
-/* $Id: dram_init.S,v 1.8 2001/05/15 07:12:45 hp Exp $
+/* $Id: dram_init.S,v 1.10 2001/10/04 12:00:21 martinnn Exp $
  * 
  * DRAM/SDRAM initialization - alter with care
  * This file is intended to be included from other assembler files
@@ -11,6 +11,12 @@
  * Authors:  Mikael Starvik (starvik@axis.com)	
  * 
  * $Log: dram_init.S,v $
+ * Revision 1.10  2001/10/04 12:00:21  martinnn
+ * Added missing underscores.
+ *
+ * Revision 1.9  2001/10/01 14:47:35  bjornw
+ * Added register prefixes and removed underscores
+ *
  * Revision 1.8  2001/05/15 07:12:45  hp
  * Copy warning from head.S about r8 and r9
  *
@@ -52,24 +58,24 @@
 	;; They should not be used in the code below.
 
 #ifndef CONFIG_SVINTO_SIM	
-	move.d   CONFIG_ETRAX_DEF_R_WAITSTATES, r0
-	move.d   r0, [R_WAITSTATES]
+	move.d   CONFIG_ETRAX_DEF_R_WAITSTATES, $r0
+	move.d   $r0, [R_WAITSTATES]
 
-	move.d   CONFIG_ETRAX_DEF_R_BUS_CONFIG, r0
-	move.d   r0, [R_BUS_CONFIG]
+	move.d   CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0
+	move.d   $r0, [R_BUS_CONFIG]
 	
 #ifndef CONFIG_ETRAX_SDRAM
-	move.d   CONFIG_ETRAX_DEF_R_DRAM_CONFIG, r0
-	move.d   r0, [R_DRAM_CONFIG]
+	move.d   CONFIG_ETRAX_DEF_R_DRAM_CONFIG, $r0
+	move.d   $r0, [R_DRAM_CONFIG]
 
-	move.d   CONFIG_ETRAX_DEF_R_DRAM_TIMING, r0
-	move.d   r0, [R_DRAM_TIMING]
+	move.d   CONFIG_ETRAX_DEF_R_DRAM_TIMING, $r0
+	move.d   $r0, [R_DRAM_TIMING]
 #else	
 	; Refer to ETRAX 100LX Designers Reference for a description of SDRAM initialization
 	
 	; Bank configuration
-	move.d   CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, r0
-	move.d   r0, [R_SDRAM_CONFIG]
+	move.d   CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r0
+	move.d   $r0, [R_SDRAM_CONFIG]
 
 	; Calculate value of mrs_data 
 	; CAS latency = 2 && bus_width = 32 => 0x40
@@ -77,71 +83,69 @@
 	; CAS latency = 2 && bus_width = 16 => 0x20
 	; CAS latency = 3 && bus_width = 16 => 0x30
 	
-	move.d   0x40, r2       ; Assume 32 bits and CAS latency = 2
-	move.d   CONFIG_ETRAX_DEF_R_SDRAM_TIMING, r1
-	move.d   r1, r3
- 	and.d    0x03, r1       ; Get CAS latency
-	and.d    0x1000, r3     ; 50 or 100 MHz?
-	beq      speed_50
-	nop
-speed_100:		
-	cmp.d    0x00, r1	; CAS latency = 2?
-	beq      bw_check
-	nop
-	or.d     0x20, r2	; CAS latency = 3 
-	ba       bw_check
-	nop
-speed_50:			
-	cmp.d    0x01, r1	; CAS latency = 2?
-	beq      bw_check
-	nop
-	or.d     0x20, r2       ; CAS latency = 3
-bw_check:
-	move.d   CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, r1
-	and.d    0x800000, r1	; DRAM width is bit 23
-	bne      set_timing
+	move.d   0x40, $r2       ; Assume 32 bits and CAS latency = 2
+	move.d   CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1
+	move.d   $r1, $r3
+ 	and.d    0x03, $r1       ; Get CAS latency
+	and.d    0x1000, $r3     ; 50 or 100 MHz?
+	beq      _speed_50
+	nop
+_speed_100:		
+	cmp.d    0x00, $r1	; CAS latency = 2?
+	beq      _bw_check
+	nop
+	or.d     0x20, $r2	; CAS latency = 3 
+	ba       _bw_check
+	nop
+_speed_50:			
+	cmp.d    0x01, $r1	; CAS latency = 2?
+	beq      _bw_check
+	nop
+	or.d     0x20, $r2       ; CAS latency = 3
+_bw_check:
+	move.d   CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r1
+	and.d    0x800000, $r1	; DRAM width is bit 23
+	bne      _set_timing
 	nop
-	lsrq     1, r2		;  16 bits. Shift down value.
+	lsrq     1, $r2		;  16 bits. Shift down value.
 
 	; Set timing parameters. Starts master clock
-set_timing:
-	move.d   CONFIG_ETRAX_DEF_R_SDRAM_TIMING, r1
-	and.d    0x8000f9ff, r1 ; Make sure mrs data and command is 0 
-	or.d     0x80000000, r1	; Make sure sdram enable bit is set
-	move.d   r1, r5
-	or.d     0x0000c000, r1 ; ref = disable
-	lslq     16, r2		; mrs data starts at bit 16
-	or.d     r2, r1 
-	move.d   r1, [R_SDRAM_TIMING]	
+_set_timing:
+	move.d   CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1
+	and.d    0x8000f9ff, $r1 ; Make sure mrs data and command is 0 
+	or.d     0x80000000, $r1	; Make sure sdram enable bit is set
+	move.d   $r1, $r5
+	or.d     0x0000c000, $r1 ; ref = disable
+	lslq     16, $r2		; mrs data starts at bit 16
+	or.d     $r2, $r1 
+	move.d   $r1, [R_SDRAM_TIMING]	
 		
 	; Wait 200us
-	move.d   10000, r2
-sdram_loop:
-	bne      sdram_loop
-	subq     1, r2
+	move.d   10000, $r2
+1:	bne      1b
+	subq     1, $r2
 	
 	; Issue initialization command sequence
-	move.d   sdram_commands_start, r2
-	move.d   sdram_commands_end,  r3
-command_loop:
-	clear.d  r4
-	move.b   [r2+], r4
-	lslq     9, r4	; Command starts at bit 9
-	or.d     r1, r4
-	move.d   r4, [R_SDRAM_TIMING]
+	move.d   _sdram_commands_start, $r2
+	move.d   _sdram_commands_end,  $r3
+1:	clear.d  $r4
+	move.b   [$r2+], $r4
+	lslq     9, $r4	; Command starts at bit 9
+	or.d     $r1, $r4
+	move.d   $r4, [R_SDRAM_TIMING]
 	nop		; Wait five nop cycles between each command
 	nop
 	nop
 	nop
 	nop
-	cmp.d    r2, r3
-	bne      command_loop
+	cmp.d    $r2, $r3
+	bne      1b
 	nop
-	move.d   r5, [R_SDRAM_TIMING]
-	ba       sdram_commands_end
+	move.d   $r5, [R_SDRAM_TIMING]
+	ba       _sdram_commands_end
 	nop
 
-sdram_commands_start:
+_sdram_commands_start:
 	.byte   3	; Precharge
 	.byte   0       ; nop
 	.byte   2	; refresh
@@ -162,6 +166,6 @@
 	.byte   0	; nop
 	.byte   1	; mrs
 	.byte   0	; nop 
-sdram_commands_end:		
+_sdram_commands_end:		
 #endif
 #endif