patch-2.4.14 linux/drivers/scsi/sun3x_esp.c

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diff -u --recursive --new-file v2.4.13/linux/drivers/scsi/sun3x_esp.c linux/drivers/scsi/sun3x_esp.c
@@ -21,6 +21,7 @@
 #include "sun3x_esp.h"
 #include <asm/sun3x.h>
 #include <asm/dvma.h>
+#include <asm/irq.h>
 
 extern struct NCR_ESP *espchain;
 
@@ -28,6 +29,7 @@
 static int  dma_bytes_sent(struct NCR_ESP *esp, int fifo_count);
 static int  dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp);
 static void dma_drain(struct NCR_ESP *esp);
+static void dma_invalidate(struct NCR_ESP *esp);
 static void dma_dump_state(struct NCR_ESP *esp);
 static void dma_init_read(struct NCR_ESP *esp, __u32 vaddress, int length);
 static void dma_init_write(struct NCR_ESP *esp, __u32 vaddress, int length);
@@ -44,7 +46,7 @@
 static void dma_mmu_release_scsi_sgl (struct NCR_ESP *esp, Scsi_Cmnd *sp);
 static void dma_advance_sg (Scsi_Cmnd *sp);
 
-volatile unsigned char cmd_buffer[16];
+static volatile unsigned char cmd_buffer[16];
                                 /* This is where all commands are put
                                  * before they are trasfered to the ESP chip
                                  * via PIO.
@@ -78,9 +80,10 @@
 
 	/* Optional functions */
 	esp->dma_barrier = &dma_barrier;
+	esp->dma_invalidate = &dma_invalidate;
 	esp->dma_drain = &dma_drain;
-	esp->dma_irq_entry = &dma_ints_off;
-	esp->dma_irq_exit = &dma_ints_on;
+	esp->dma_irq_entry = 0;
+	esp->dma_irq_exit = 0;
 	esp->dma_led_on = 0;
 	esp->dma_led_off = 0;
 	esp->dma_poll = &dma_poll;
@@ -98,9 +101,14 @@
 	esp->eregs = (struct ESP_regs *)(SUN3X_ESP_BASE);
 	esp->dregs = (void *)SUN3X_ESP_DMA;
 
-	esp->esp_command = (volatile unsigned char *)cmd_buffer;
-	esp->esp_command_dvma = dvma_alloc(virt_to_phys(cmd_buffer), 
-					   sizeof (cmd_buffer));
+#if 0
+  	esp->esp_command = (volatile unsigned char *)cmd_buffer;
+ 	esp->esp_command_dvma = dvma_map((unsigned long)cmd_buffer,
+ 					 sizeof (cmd_buffer));
+#else
+	esp->esp_command = (volatile unsigned char *)dvma_malloc(DVMA_PAGE_SIZE);
+	esp->esp_command_dvma = dvma_vtob((unsigned long)esp->esp_command);
+#endif
 
 	esp->irq = 2;
 	if (request_irq(esp->irq, esp_intr, SA_INTERRUPT, 
@@ -114,20 +122,57 @@
 
 	esp_initialize(esp);
 
+ 	/* for reasons beyond my knowledge (and which should likely be fixed)
+ 	   sync mode doesn't work on a 3/80 at 5mhz.  but it does at 4. */
+ 	esp->sync_defp = 0x3f;
+
 	printk("ESP: Total of %d ESP hosts found, %d actually in use.\n", nesps,
 	       esps_in_use);
 	esps_running = esps_in_use;
 	return esps_in_use;
 }
 
+static void dma_do_drain(struct NCR_ESP *esp)
+{
+ 	struct sparc_dma_registers *dregs =
+ 		(struct sparc_dma_registers *) esp->dregs;
+ 	
+ 	int count = 500000;
+ 
+ 	while((dregs->cond_reg & DMA_PEND_READ) && (--count > 0)) 
+ 		udelay(1);
+ 
+ 	if(!count) {
+ 		printk("%s:%d timeout CSR %08lx\n", __FILE__, __LINE__, dregs->cond_reg);
+ 	}
+ 
+ 	dregs->cond_reg |= DMA_FIFO_STDRAIN;
+ 	
+ 	count = 500000;
+ 
+ 	while((dregs->cond_reg & DMA_FIFO_ISDRAIN) && (--count > 0)) 
+ 		udelay(1);
+ 
+ 	if(!count) {
+ 		printk("%s:%d timeout CSR %08lx\n", __FILE__, __LINE__, dregs->cond_reg);
+ 	}
+ 
+}
+ 
 static void dma_barrier(struct NCR_ESP *esp)
 {
-	struct sparc_dma_registers *dregs =
-		(struct sparc_dma_registers *) esp->dregs;
-
-	while(dregs->cond_reg & DMA_PEND_READ)
-		udelay(1);
-	dregs->cond_reg &= ~(DMA_ENABLE);
+  	struct sparc_dma_registers *dregs =
+  		(struct sparc_dma_registers *) esp->dregs;
+ 	int count = 500000;
+  
+ 	while((dregs->cond_reg & DMA_PEND_READ) && (--count > 0))
+  		udelay(1);
+ 
+ 	if(!count) {
+ 		printk("%s:%d timeout CSR %08lx\n", __FILE__, __LINE__, dregs->cond_reg);
+ 	}
+ 
+  	dregs->cond_reg &= ~(DMA_ENABLE);
 }
 
 /* This uses various DMA csr fields and the fifo flags count value to
@@ -145,27 +190,44 @@
 
 static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp)
 {
-	__u32 base, end, sz;
-
-	base = ((__u32)sp->SCp.ptr);
-	base &= (0x1000000 - 1);
-	end = (base + sp->SCp.this_residual);
-	if(end > 0x1000000)
-		end = 0x1000000;
-	sz = (end - base);
-	return sz;
+	return sp->SCp.this_residual;
 }
 
 static void dma_drain(struct NCR_ESP *esp)
 {
 	struct sparc_dma_registers *dregs =
 		(struct sparc_dma_registers *) esp->dregs;
+	int count = 500000;
 
 	if(dregs->cond_reg & DMA_FIFO_ISDRAIN) {
 		dregs->cond_reg |= DMA_FIFO_STDRAIN;
-		while(dregs->cond_reg & DMA_FIFO_ISDRAIN)
+		while((dregs->cond_reg & DMA_FIFO_ISDRAIN) && (--count > 0))
 			udelay(1);
+		if(!count) {
+			printk("%s:%d timeout CSR %08lx\n", __FILE__, __LINE__, dregs->cond_reg);
+		}
+
+	}
+}
+
+static void dma_invalidate(struct NCR_ESP *esp)
+{
+	struct sparc_dma_registers *dregs =
+		(struct sparc_dma_registers *) esp->dregs;
+
+	__u32 tmp;
+	int count = 500000;
+
+	while(((tmp = dregs->cond_reg) & DMA_PEND_READ) && (--count > 0)) 
+		udelay(1);
+
+	if(!count) {
+		printk("%s:%d timeout CSR %08lx\n", __FILE__, __LINE__, dregs->cond_reg);
 	}
+
+	dregs->cond_reg = tmp | DMA_FIFO_INV;
+	dregs->cond_reg &= ~DMA_FIFO_INV;
+
 }
 
 static void dma_dump_state(struct NCR_ESP *esp)
@@ -173,7 +235,7 @@
 	struct sparc_dma_registers *dregs =
 		(struct sparc_dma_registers *) esp->dregs;
 
-	ESPLOG(("esp%d: dma -- cond_reg<%08lx> addr<%p>\n",
+	ESPLOG(("esp%d: dma -- cond_reg<%08lx> addr<%08lx>\n",
 		esp->esp_id, dregs->cond_reg, dregs->st_addr));
 }
 
@@ -182,8 +244,8 @@
 	struct sparc_dma_registers *dregs = 
 		(struct sparc_dma_registers *) esp->dregs;
 
-	dregs->cond_reg |= (DMA_ST_WRITE | DMA_ENABLE);
 	dregs->st_addr = vaddress;
+	dregs->cond_reg |= (DMA_ST_WRITE | DMA_ENABLE);
 }
 
 static void dma_init_write(struct NCR_ESP *esp, __u32 vaddress, int length)
@@ -192,8 +254,9 @@
 		(struct sparc_dma_registers *) esp->dregs;
 
 	/* Set up the DMA counters */
-	dregs->cond_reg = ((dregs->cond_reg & ~(DMA_ST_WRITE)) | DMA_ENABLE);
+
 	dregs->st_addr = vaddress;
+	dregs->cond_reg = ((dregs->cond_reg & ~(DMA_ST_WRITE)) | DMA_ENABLE);
 }
 
 static void dma_ints_off(struct NCR_ESP *esp)
@@ -213,11 +276,21 @@
 
 static void dma_poll(struct NCR_ESP *esp, unsigned char *vaddr)
 {
-	dma_drain(esp);
+	int count = 50;
+	dma_do_drain(esp);
 
 	/* Wait till the first bits settle. */
-	while(vaddr[0] == 0xff)
+	while((*(volatile unsigned char *)vaddr == 0xff) && (--count > 0))
 		udelay(1);
+
+	if(!count) {
+//		printk("%s:%d timeout expire (data %02x)\n", __FILE__, __LINE__,
+//		       esp_read(esp->eregs->esp_fdata));
+		//mach_halt();
+		vaddr[0] = esp_read(esp->eregs->esp_fdata);
+		vaddr[1] = esp_read(esp->eregs->esp_fdata);
+	}
+
 }	
 
 static int dma_ports_p(struct NCR_ESP *esp)
@@ -244,10 +317,17 @@
 		(struct sparc_dma_registers *) esp->dregs;
 	unsigned long nreg = dregs->cond_reg;
 
+//	printk("dma_setup %c addr %08x cnt %08x\n",
+//	       write ? 'W' : 'R', addr, count);
+
+	dma_do_drain(esp);
+
 	if(write)
 		nreg |= DMA_ST_WRITE;
-	else
+	else {
 		nreg &= ~(DMA_ST_WRITE);
+	}
+		
 	nreg |= DMA_ENABLE;
 	dregs->cond_reg = nreg;
 	dregs->st_addr = addr;
@@ -255,7 +335,7 @@
 
 static void dma_mmu_get_scsi_one (struct NCR_ESP *esp, Scsi_Cmnd *sp)
 {
-    sp->SCp.have_data_in = dvma_alloc(virt_to_phys(sp->SCp.buffer),
+    sp->SCp.have_data_in = dvma_map((unsigned long)sp->SCp.buffer,
 				       sp->SCp.this_residual);
     sp->SCp.ptr = (char *)((unsigned long)sp->SCp.have_data_in);
 }
@@ -266,7 +346,7 @@
     struct mmu_sglist *sg = (struct mmu_sglist *) sp->SCp.buffer;
 
     while (sz >= 0) {
-        sg[sz].dvma_addr = dvma_alloc(virt_to_phys(sg[sz].addr), sg[sz].len);
+        sg[sz].dvma_addr = dvma_map((unsigned long)sg[sz].addr, sg[sz].len);
         sz--;
     }
     sp->SCp.ptr=(char *)((unsigned long)sp->SCp.buffer->dvma_address);
@@ -274,7 +354,7 @@
 
 static void dma_mmu_release_scsi_one (struct NCR_ESP *esp, Scsi_Cmnd *sp)
 {
-    dvma_free(sp->SCp.have_data_in, sp->request_bufflen);
+    dvma_unmap(sp->SCp.have_data_in);
 }
 
 static void dma_mmu_release_scsi_sgl (struct NCR_ESP *esp, Scsi_Cmnd *sp)
@@ -283,7 +363,7 @@
     struct mmu_sglist *sg = (struct mmu_sglist *)sp->buffer;
                         
     while(sz >= 0) {
-        dvma_free(sg[sz].dvma_addr,sg[sz].len);
+        dvma_unmap(sg[sz].dvma_addr);
         sz--;
     }
 }

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