patch-2.4.15 linux/include/asm-ia64/spinlock.h

• Lines: 89
• Date: Fri Nov 9 14:26:17 2001
• Orig file: v2.4.14/linux/include/asm-ia64/spinlock.h
• Orig date: Sun Aug 12 13:28:00 2001

diff -u --recursive --new-file v2.4.14/linux/include/asm-ia64/spinlock.h linux/include/asm-ia64/spinlock.h
@@ -2,8 +2,8 @@
 #define _ASM_IA64_SPINLOCK_H
 
 /*
- * Copyright (C) 1998-2000 Hewlett-Packard Co
- * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1998-2001 Hewlett-Packard Co
+ * Copyright (C) 1998-2001 David Mosberger-Tang <davidm@hpl.hp.com>
  * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
  *
  * This file is used for SMP configurations only.
@@ -39,7 +39,7 @@
 		"mov r30=1\n"								\
 		"mov ar.ccv=r0\n"							\
 		";;\n"									\
-		IA64_SEMFIX"cmpxchg4.acq r30=[%0],r30,ar.ccv\n"				\
+		"cmpxchg4.acq r30=[%0],r30,ar.ccv\n"					\
 		";;\n"									\
 		"cmp.ne p15,p0=r30,r0\n"						\
 		"(p15) br.call.spnt.few b7=ia64_spinlock_contention\n"			\
@@ -56,7 +56,7 @@
 	__asm__ __volatile__ (								\
 		"mov ar.ccv=r0\n"							\
 		";;\n"									\
-		IA64_SEMFIX"cmpxchg4.acq %0=[%2],%1,ar.ccv\n"				\
+		"cmpxchg4.acq %0=[%2],%1,ar.ccv\n"					\
 		: "=r"(result) : "r"(1), "r"(&(x)->lock) : "ar.ccv", "memory");		\
 	(result == 0);									\
 })
@@ -84,11 +84,11 @@
 	"mov r29 = 1\n"						\
 	";;\n"							\
 	"1:\n"							\
-	"ld4 r2 = [%0]\n"					\
+	"ld4.bias r2 = [%0]\n"					\
 	";;\n"							\
 	"cmp4.eq p0,p7 = r0,r2\n"				\
 	"(p7) br.cond.spnt.few 1b \n"				\
-	IA64_SEMFIX"cmpxchg4.acq r2 = [%0], r29, ar.ccv\n"	\
+	"cmpxchg4.acq r2 = [%0], r29, ar.ccv\n"			\
 	";;\n"							\
 	"cmp4.eq p0,p7 = r0, r2\n"				\
 	"(p7) br.cond.spnt.few 1b\n"				\
@@ -108,15 +108,17 @@
 } rwlock_t;
 #define RW_LOCK_UNLOCKED (rwlock_t) { 0, 0 }
 
+#define rwlock_init(x) do { *(x) = RW_LOCK_UNLOCKED; } while(0)
+
 #define read_lock(rw)								\
 do {										\
 	int tmp = 0;								\
-	__asm__ __volatile__ ("1:\t"IA64_SEMFIX"fetchadd4.acq %0 = [%1], 1\n"	\
+	__asm__ __volatile__ ("1:\tfetchadd4.acq %0 = [%1], 1\n"		\
 			      ";;\n"						\
 			      "tbit.nz p6,p0 = %0, 31\n"			\
 			      "(p6) br.cond.sptk.few 2f\n"			\
 			      ".section .text.lock,\"ax\"\n"			\
-			      "2:\t"IA64_SEMFIX"fetchadd4.rel %0 = [%1], -1\n"	\
+			      "2:\tfetchadd4.rel %0 = [%1], -1\n"		\
 			      ";;\n"						\
 			      "3:\tld4.acq %0 = [%1]\n"				\
 			      ";;\n"						\
@@ -132,7 +134,7 @@
 #define read_unlock(rw)								\
 do {										\
 	int tmp = 0;								\
-	__asm__ __volatile__ (IA64_SEMFIX"fetchadd4.rel %0 = [%1], -1\n"	\
+	__asm__ __volatile__ ("fetchadd4.rel %0 = [%1], -1\n"			\
 			      : "=r" (tmp)					\
 			      : "r" (rw)					\
 			      : "memory");					\
@@ -142,14 +144,14 @@
 do {										\
  	__asm__ __volatile__ (							\
 		"mov ar.ccv = r0\n"						\
-		"movl r29 = 0x80000000\n"					\
+		"dep r29 = -1, r0, 31, 1\n"					\
 		";;\n"								\
 		"1:\n"								\
 		"ld4 r2 = [%0]\n"						\
 		";;\n"								\
 		"cmp4.eq p0,p7 = r0,r2\n"					\
 		"(p7) br.cond.spnt.few 1b \n"					\
-		IA64_SEMFIX"cmpxchg4.acq r2 = [%0], r29, ar.ccv\n"		\
+		"cmpxchg4.acq r2 = [%0], r29, ar.ccv\n"				\
 		";;\n"								\
 		"cmp4.eq p0,p7 = r0, r2\n"					\
 		"(p7) br.cond.spnt.few 1b\n"					\