patch-2.4.21 linux-2.4.21/arch/x86_64/kernel/nmi.c

• Lines: 92
• Date: 2003-06-13 07:51:32.000000000 -0700
• Orig file: linux-2.4.20/arch/x86_64/kernel/nmi.c
• Orig date: 2002-11-28 15:53:12.000000000 -0800

diff -urN linux-2.4.20/arch/x86_64/kernel/nmi.c linux-2.4.21/arch/x86_64/kernel/nmi.c
@@ -31,6 +31,8 @@
 static unsigned int nmi_hz = HZ;
 unsigned int nmi_perfctr_msr;	/* the MSR to reset in NMI handler */
 
+int nmi_watchdog_disabled; 
+
 #define K7_EVNTSEL_ENABLE	(1 << 22)
 #define K7_EVNTSEL_INT		(1 << 20)
 #define K7_EVNTSEL_OS		(1 << 17)
@@ -223,6 +225,7 @@
 	wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
 }
 
+#ifndef CONFIG_MK8
 static void __pminit setup_p6_watchdog(void)
 {
 	unsigned int evntsel;
@@ -274,6 +277,7 @@
 	wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0, 0);
 	return 1;
 }
+#endif
 
 void __pminit setup_apic_nmi_watchdog (void)
 {
@@ -285,6 +289,7 @@
 			return;	    
 		setup_k7_watchdog();
 		break;
+#ifndef CONFIG_MK8
 	case X86_VENDOR_INTEL:
 		switch (boot_cpu_data.x86) {
 		case 6:
@@ -298,6 +303,7 @@
 			return;
 		}
 		break;
+#endif
 	default:
 		return;
 	}
@@ -337,14 +343,17 @@
 		alert_counter[i] = 0;
 }
 
-void nmi_watchdog_tick (struct pt_regs * regs)
+void nmi_watchdog_tick (struct pt_regs * regs, unsigned reason)
 {
 
 	/*
 	 * Since current-> is always on the stack, and we always switch
 	 * the stack NMI-atomically, it's safe to use smp_processor_id().
 	 */
-	int sum, cpu = smp_processor_id();
+	int sum, cpu = safe_smp_processor_id();
+
+	if (nmi_watchdog_disabled)
+		return;
 
 	sum = apic_timer_irqs[cpu];
 
@@ -355,6 +364,14 @@
 		 */
 		alert_counter[cpu]++;
 		if (alert_counter[cpu] == 5*nmi_hz) {
+
+
+			if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT) == NOTIFY_BAD) { 
+				alert_counter[cpu] = 0; 
+				return;
+			} 
+
+
 			spin_lock(&nmi_print_lock);
 			/*
 			 * We are in trouble anyway, lets at least try
@@ -374,6 +391,7 @@
 		alert_counter[cpu] = 0;
 	}
 	if (nmi_perfctr_msr) {
+#ifndef CONFIG_MK8
 		if (nmi_perfctr_msr == MSR_P4_IQ_COUNTER0) {
 			/*
 			 * P4 quirks:
@@ -385,6 +403,7 @@
 			wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0, 0);
 			apic_write(APIC_LVTPC, APIC_DM_NMI);
 		}
+#endif
 		wrmsr(nmi_perfctr_msr, -(cpu_khz/nmi_hz*1000), -1);
 	}
 }