patch-2.4.23 linux-2.4.23/arch/sh64/kernel/fpu.c
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- Lines: 183
- Date:
2003-11-28 10:26:19.000000000 -0800
- Orig file:
linux-2.4.22/arch/sh64/kernel/fpu.c
- Orig date:
2003-08-25 04:44:40.000000000 -0700
diff -urN linux-2.4.22/arch/sh64/kernel/fpu.c linux-2.4.23/arch/sh64/kernel/fpu.c
@@ -23,47 +23,56 @@
* has the property that no matter whether considered as single or as
* double precision, it still represents a signalling NAN.
*/
-#define sNAN64 0xFFFFFFFFFFFFFFFF
+#define sNAN64 0xFFFFFFFFFFFFFFFFULL
+#define sNAN32 0xFFFFFFFFUL
+static union sh_fpu_union init_fpuregs = {
+ .hard = {
+ .fp_regs = { [0 ... 63] = sNAN32 },
+ .fpscr = FPSCR_INIT
+ }
+};
+#if 0
static struct sh_fpu_hard_struct init_fpuregs = {
- { [0 ... 31] = sNAN64 },
+ { [0 ... 63] = sNAN32 },
FPSCR_INIT
};
+#endif
inline void fpsave(struct sh_fpu_hard_struct *fpregs)
{
- asm volatile("fst.d %0, (0*8)," __d(0) "\n\t"
- "fst.d %0, (1*8)," __d(2) "\n\t"
- "fst.d %0, (2*8)," __d(4) "\n\t"
- "fst.d %0, (3*8)," __d(6) "\n\t"
- "fst.d %0, (4*8)," __d(8) "\n\t"
- "fst.d %0, (5*8)," __d(10) "\n\t"
- "fst.d %0, (6*8)," __d(12) "\n\t"
- "fst.d %0, (7*8)," __d(14) "\n\t"
- "fst.d %0, (8*8)," __d(16) "\n\t"
- "fst.d %0, (9*8)," __d(18) "\n\t"
- "fst.d %0, (10*8)," __d(20) "\n\t"
- "fst.d %0, (11*8)," __d(22) "\n\t"
- "fst.d %0, (12*8)," __d(24) "\n\t"
- "fst.d %0, (13*8)," __d(26) "\n\t"
- "fst.d %0, (14*8)," __d(28) "\n\t"
- "fst.d %0, (15*8)," __d(30) "\n\t"
- "fst.d %0, (16*8)," __d(32) "\n\t"
- "fst.d %0, (17*8)," __d(34) "\n\t"
- "fst.d %0, (18*8)," __d(36) "\n\t"
- "fst.d %0, (19*8)," __d(38) "\n\t"
- "fst.d %0, (20*8)," __d(40) "\n\t"
- "fst.d %0, (21*8)," __d(42) "\n\t"
- "fst.d %0, (22*8)," __d(44) "\n\t"
- "fst.d %0, (23*8)," __d(46) "\n\t"
- "fst.d %0, (24*8)," __d(48) "\n\t"
- "fst.d %0, (25*8)," __d(50) "\n\t"
- "fst.d %0, (26*8)," __d(52) "\n\t"
- "fst.d %0, (27*8)," __d(54) "\n\t"
- "fst.d %0, (28*8)," __d(56) "\n\t"
- "fst.d %0, (29*8)," __d(58) "\n\t"
- "fst.d %0, (30*8)," __d(60) "\n\t"
- "fst.d %0, (31*8)," __d(62) "\n\t"
+ asm volatile("fst.p %0, (0*8)," __p(0) "\n\t"
+ "fst.p %0, (1*8)," __p(2) "\n\t"
+ "fst.p %0, (2*8)," __p(4) "\n\t"
+ "fst.p %0, (3*8)," __p(6) "\n\t"
+ "fst.p %0, (4*8)," __p(8) "\n\t"
+ "fst.p %0, (5*8)," __p(10) "\n\t"
+ "fst.p %0, (6*8)," __p(12) "\n\t"
+ "fst.p %0, (7*8)," __p(14) "\n\t"
+ "fst.p %0, (8*8)," __p(16) "\n\t"
+ "fst.p %0, (9*8)," __p(18) "\n\t"
+ "fst.p %0, (10*8)," __p(20) "\n\t"
+ "fst.p %0, (11*8)," __p(22) "\n\t"
+ "fst.p %0, (12*8)," __p(24) "\n\t"
+ "fst.p %0, (13*8)," __p(26) "\n\t"
+ "fst.p %0, (14*8)," __p(28) "\n\t"
+ "fst.p %0, (15*8)," __p(30) "\n\t"
+ "fst.p %0, (16*8)," __p(32) "\n\t"
+ "fst.p %0, (17*8)," __p(34) "\n\t"
+ "fst.p %0, (18*8)," __p(36) "\n\t"
+ "fst.p %0, (19*8)," __p(38) "\n\t"
+ "fst.p %0, (20*8)," __p(40) "\n\t"
+ "fst.p %0, (21*8)," __p(42) "\n\t"
+ "fst.p %0, (22*8)," __p(44) "\n\t"
+ "fst.p %0, (23*8)," __p(46) "\n\t"
+ "fst.p %0, (24*8)," __p(48) "\n\t"
+ "fst.p %0, (25*8)," __p(50) "\n\t"
+ "fst.p %0, (26*8)," __p(52) "\n\t"
+ "fst.p %0, (27*8)," __p(54) "\n\t"
+ "fst.p %0, (28*8)," __p(56) "\n\t"
+ "fst.p %0, (29*8)," __p(58) "\n\t"
+ "fst.p %0, (30*8)," __p(60) "\n\t"
+ "fst.p %0, (31*8)," __p(62) "\n\t"
"_fgetscr " __f(63) "\n\t"
"fst.s %0, (32*8)," __f(63) "\n\t"
@@ -76,49 +85,49 @@
static inline void
fpload(struct sh_fpu_hard_struct *fpregs)
{
- asm volatile("fld.d %0, (0*8)," __d(0) "\n\t"
- "fld.d %0, (1*8)," __d(2) "\n\t"
- "fld.d %0, (2*8)," __d(4) "\n\t"
- "fld.d %0, (3*8)," __d(6) "\n\t"
- "fld.d %0, (4*8)," __d(8) "\n\t"
- "fld.d %0, (5*8)," __d(10) "\n\t"
- "fld.d %0, (6*8)," __d(12) "\n\t"
- "fld.d %0, (7*8)," __d(14) "\n\t"
- "fld.d %0, (8*8)," __d(16) "\n\t"
- "fld.d %0, (9*8)," __d(18) "\n\t"
- "fld.d %0, (10*8)," __d(20) "\n\t"
- "fld.d %0, (11*8)," __d(22) "\n\t"
- "fld.d %0, (12*8)," __d(24) "\n\t"
- "fld.d %0, (13*8)," __d(26) "\n\t"
- "fld.d %0, (14*8)," __d(28) "\n\t"
- "fld.d %0, (15*8)," __d(30) "\n\t"
- "fld.d %0, (16*8)," __d(32) "\n\t"
- "fld.d %0, (17*8)," __d(34) "\n\t"
- "fld.d %0, (18*8)," __d(36) "\n\t"
- "fld.d %0, (19*8)," __d(38) "\n\t"
- "fld.d %0, (20*8)," __d(40) "\n\t"
- "fld.d %0, (21*8)," __d(42) "\n\t"
- "fld.d %0, (22*8)," __d(44) "\n\t"
- "fld.d %0, (23*8)," __d(46) "\n\t"
- "fld.d %0, (24*8)," __d(48) "\n\t"
- "fld.d %0, (25*8)," __d(50) "\n\t"
- "fld.d %0, (26*8)," __d(52) "\n\t"
- "fld.d %0, (27*8)," __d(54) "\n\t"
- "fld.d %0, (28*8)," __d(56) "\n\t"
- "fld.d %0, (29*8)," __d(58) "\n\t"
- "fld.d %0, (30*8)," __d(60) "\n\t"
+ asm volatile("fld.p %0, (0*8)," __p(0) "\n\t"
+ "fld.p %0, (1*8)," __p(2) "\n\t"
+ "fld.p %0, (2*8)," __p(4) "\n\t"
+ "fld.p %0, (3*8)," __p(6) "\n\t"
+ "fld.p %0, (4*8)," __p(8) "\n\t"
+ "fld.p %0, (5*8)," __p(10) "\n\t"
+ "fld.p %0, (6*8)," __p(12) "\n\t"
+ "fld.p %0, (7*8)," __p(14) "\n\t"
+ "fld.p %0, (8*8)," __p(16) "\n\t"
+ "fld.p %0, (9*8)," __p(18) "\n\t"
+ "fld.p %0, (10*8)," __p(20) "\n\t"
+ "fld.p %0, (11*8)," __p(22) "\n\t"
+ "fld.p %0, (12*8)," __p(24) "\n\t"
+ "fld.p %0, (13*8)," __p(26) "\n\t"
+ "fld.p %0, (14*8)," __p(28) "\n\t"
+ "fld.p %0, (15*8)," __p(30) "\n\t"
+ "fld.p %0, (16*8)," __p(32) "\n\t"
+ "fld.p %0, (17*8)," __p(34) "\n\t"
+ "fld.p %0, (18*8)," __p(36) "\n\t"
+ "fld.p %0, (19*8)," __p(38) "\n\t"
+ "fld.p %0, (20*8)," __p(40) "\n\t"
+ "fld.p %0, (21*8)," __p(42) "\n\t"
+ "fld.p %0, (22*8)," __p(44) "\n\t"
+ "fld.p %0, (23*8)," __p(46) "\n\t"
+ "fld.p %0, (24*8)," __p(48) "\n\t"
+ "fld.p %0, (25*8)," __p(50) "\n\t"
+ "fld.p %0, (26*8)," __p(52) "\n\t"
+ "fld.p %0, (27*8)," __p(54) "\n\t"
+ "fld.p %0, (28*8)," __p(56) "\n\t"
+ "fld.p %0, (29*8)," __p(58) "\n\t"
+ "fld.p %0, (30*8)," __p(60) "\n\t"
"fld.s %0, (32*8)," __f(63) "\n\t"
"_fputscr " __f(63) "\n\t"
- "fld.d %0, (31*8)," __d(62) "\n\t"
+ "fld.p %0, (31*8)," __p(62) "\n\t"
: /* no output */
: "r" (fpregs) );
}
void fpinit(struct sh_fpu_hard_struct *fpregs)
{
- *fpregs = init_fpuregs;
+ *fpregs = init_fpuregs.hard;
}
asmlinkage void
@@ -163,7 +172,7 @@
fpload(¤t->thread.fpu.hard);
} else {
/* First time FPU user. */
- fpload(&init_fpuregs);
+ fpload(&init_fpuregs.hard);
current->used_math = 1;
}
release_fpu();
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TCL-scripts by Sam Shen (who was at: slshen@lbl.gov)