patch-2.4.23 linux-2.4.23/arch/sh/kernel/fpu.c

• Lines: 50
• Date: 2003-11-28 10:26:19.000000000 -0800
• Orig file: linux-2.4.22/arch/sh/kernel/fpu.c
• Orig date: 2003-08-25 04:44:40.000000000 -0700

diff -urN linux-2.4.22/arch/sh/kernel/fpu.c linux-2.4.23/arch/sh/kernel/fpu.c
@@ -18,6 +18,14 @@
 #include <asm/processor.h>
 #include <asm/io.h>
 
+/* The PR (precision) bit in the FP Status Register must be clear when
+ * an frchg instruction is executed, otherwise the instruction is undefined.
+ * Executing frchg with PR set causes a trap on some SH4 implementations.
+ */
+
+#define FPSCR_RCHG 0x00000000
+
+
 /*
  * Save FPU registers onto task structure.
  * Assume called with FPU enabled (SR.FD=0).
@@ -61,9 +69,11 @@
 		     "fmov.s	fr3, @-%0\n\t"
 		     "fmov.s	fr2, @-%0\n\t"
 		     "fmov.s	fr1, @-%0\n\t"
-		     "fmov.s	fr0, @-%0"
+		     "fmov.s	fr0, @-%0\n\t"
+		     "lds	%2, fpscr\n\t"
 		     : /* no output */
 		     : "r" ((char *)(&tsk->thread.fpu.hard.status)),
+		       "r" (FPSCR_RCHG),
 		       "r" (FPSCR_INIT)
 		     : "memory");
 
@@ -112,7 +122,7 @@
 		     "lds.l	@%0+, fpscr\n\t"
 		     "lds.l	@%0+, fpul\n\t"
 		     : /* no output */
-		     : "r" (&tsk->thread.fpu), "r" (FPSCR_INIT)
+		     : "r" (&tsk->thread.fpu), "r" (FPSCR_RCHG)
 		     : "memory");
 }
 
@@ -160,9 +170,10 @@
 		     "fsts	fpul, fr13\n\t"
 		     "fsts	fpul, fr14\n\t"
 		     "fsts	fpul, fr15\n\t"
-		     "frchg"
+		     "frchg\n\t"
+		     "lds	%2, fpscr\n\t"
 		     : /* no output */
-		     : "r" (0), "r" (FPSCR_INIT));
+		     : "r" (0), "r" (FPSCR_RCHG), "r" (FPSCR_INIT));
 }
 
 /**