patch-2.4.27 linux-2.4.27/drivers/net/e1000/e1000_hw.c
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- Lines: 1339
- Date:
2004-08-07 16:26:05.101365145 -0700
- Orig file:
linux-2.4.26/drivers/net/e1000/e1000_hw.c
- Orig date:
2004-04-14 06:05:30.000000000 -0700
diff -urN linux-2.4.26/drivers/net/e1000/e1000_hw.c linux-2.4.27/drivers/net/e1000/e1000_hw.c
@@ -65,6 +65,7 @@
static void e1000_standby_eeprom(struct e1000_hw *hw);
static int32_t e1000_id_led_init(struct e1000_hw * hw);
static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
+static int32_t e1000_set_phy_mode(struct e1000_hw *hw);
/* IGP cable length table */
static const
@@ -264,6 +265,17 @@
return -E1000_ERR_MAC_TYPE;
}
+ switch(hw->mac_type) {
+ case e1000_82541:
+ case e1000_82547:
+ case e1000_82541_rev_2:
+ case e1000_82547_rev_2:
+ hw->asf_firmware_present = TRUE;
+ break;
+ default:
+ break;
+ }
+
return E1000_SUCCESS;
}
@@ -469,11 +481,11 @@
uint16_t pcix_stat_hi_word;
uint16_t cmd_mmrbc;
uint16_t stat_mmrbc;
-
DEBUGFUNC("e1000_init_hw");
/* Initialize Identification LED */
- if((ret_val = e1000_id_led_init(hw))) {
+ ret_val = e1000_id_led_init(hw);
+ if(ret_val) {
DEBUGOUT("Error Initializing Identification LED\n");
return ret_val;
}
@@ -594,16 +606,16 @@
return E1000_SUCCESS;
}
- if ((ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
- &eeprom_data))) {
+ ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
+ if (ret_val) {
return ret_val;
}
if(eeprom_data != EEPROM_RESERVED_WORD) {
/* Adjust SERDES output amplitude only. */
eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
- if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL,
- eeprom_data)))
+ ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
+ if(ret_val)
return ret_val;
}
@@ -752,14 +764,16 @@
if(hw->media_type == e1000_media_type_fiber)
signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
- if((ret_val = e1000_adjust_serdes_amplitude(hw)))
+ ret_val = e1000_adjust_serdes_amplitude(hw);
+ if(ret_val)
return ret_val;
/* Take the link out of reset */
ctrl &= ~(E1000_CTRL_LRST);
/* Adjust VCO speed to improve BER performance */
- if((ret_val = e1000_set_vco_speed(hw)))
+ ret_val = e1000_set_vco_speed(hw);
+ if(ret_val)
return ret_val;
e1000_config_collision_dist(hw);
@@ -846,7 +860,8 @@
* we detect a signal. This will allow us to communicate with
* non-autonegotiating link partners.
*/
- if((ret_val = e1000_check_for_link(hw))) {
+ ret_val = e1000_check_for_link(hw);
+ if(ret_val) {
DEBUGOUT("Error while checking for link\n");
return ret_val;
}
@@ -893,12 +908,24 @@
}
/* Make sure we have a valid PHY */
- if((ret_val = e1000_detect_gig_phy(hw))) {
+ ret_val = e1000_detect_gig_phy(hw);
+ if(ret_val) {
DEBUGOUT("Error, did not detect valid phy.\n");
return ret_val;
}
DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
+ /* Set PHY to class A mode (if necessary) */
+ ret_val = e1000_set_phy_mode(hw);
+ if(ret_val)
+ return ret_val;
+
+ if(hw->mac_type == e1000_82545_rev_3) {
+ ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
+ phy_data |= 0x00000008;
+ ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
+ }
+
if(hw->mac_type <= e1000_82543 ||
hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
@@ -907,7 +934,8 @@
if(!hw->phy_reset_disable) {
if (hw->phy_type == e1000_phy_igp) {
- if((ret_val = e1000_phy_reset(hw))) {
+ ret_val = e1000_phy_reset(hw);
+ if(ret_val) {
DEBUGOUT("Error Resetting the PHY\n");
return ret_val;
}
@@ -922,14 +950,16 @@
E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
/* disable lplu d3 during driver init */
- if((ret_val = e1000_set_d3_lplu_state(hw, FALSE))) {
+ ret_val = e1000_set_d3_lplu_state(hw, FALSE);
+ if(ret_val) {
DEBUGOUT("Error Disabling LPLU D3\n");
return ret_val;
}
/* Configure mdi-mdix settings */
- if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
- &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
+ &phy_data);
+ if(ret_val)
return ret_val;
if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
@@ -956,8 +986,9 @@
break;
}
}
- if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
- phy_data)))
+ ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
+ phy_data);
+ if(ret_val)
return ret_val;
/* set auto-master slave resolution settings */
@@ -975,27 +1006,28 @@
* resolution as hardware default. */
if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
/* Disable SmartSpeed */
- if((ret_val = e1000_read_phy_reg(hw,
- IGP01E1000_PHY_PORT_CONFIG,
- &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
+ &phy_data);
+ if(ret_val)
return ret_val;
phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
- if((ret_val = e1000_write_phy_reg(hw,
- IGP01E1000_PHY_PORT_CONFIG,
- phy_data)))
+ ret_val = e1000_write_phy_reg(hw,
+ IGP01E1000_PHY_PORT_CONFIG,
+ phy_data);
+ if(ret_val)
return ret_val;
/* Set auto Master/Slave resolution process */
- if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
- &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
+ if(ret_val)
return ret_val;
phy_data &= ~CR_1000T_MS_ENABLE;
- if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
- phy_data)))
+ ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
+ if(ret_val)
return ret_val;
}
- if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
- &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
+ if(ret_val)
return ret_val;
/* load defaults for future use */
@@ -1018,14 +1050,15 @@
default:
break;
}
- if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
- phy_data)))
+ ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
+ if(ret_val)
return ret_val;
}
} else {
/* Enable CRS on TX. This must be set for half-duplex operation. */
- if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
- &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
+ &phy_data);
+ if(ret_val)
return ret_val;
phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
@@ -1064,15 +1097,17 @@
phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
if(hw->disable_polarity_correction == 1)
phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
- if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
- phy_data)))
+ ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
+ phy_data);
+ if(ret_val)
return ret_val;
/* Force TX_CLK in the Extended PHY Specific Control Register
* to 25MHz clock.
*/
- if((ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
- &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
+ &phy_data);
+ if(ret_val)
return ret_val;
phy_data |= M88E1000_EPSCR_TX_CLK_25;
@@ -1083,14 +1118,15 @@
M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
- if((ret_val = e1000_write_phy_reg(hw,
- M88E1000_EXT_PHY_SPEC_CTRL,
- phy_data)))
+ ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
+ phy_data);
+ if(ret_val)
return ret_val;
}
/* SW Reset the PHY so all changes take effect */
- if((ret_val = e1000_phy_reset(hw))) {
+ ret_val = e1000_phy_reset(hw);
+ if(ret_val) {
DEBUGOUT("Error Resetting the PHY\n");
return ret_val;
}
@@ -1124,7 +1160,8 @@
hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
- if((ret_val = e1000_phy_setup_autoneg(hw))) {
+ ret_val = e1000_phy_setup_autoneg(hw);
+ if(ret_val) {
DEBUGOUT("Error Setting up Auto-Negotiation\n");
return ret_val;
}
@@ -1133,18 +1170,21 @@
/* Restart auto-negotiation by setting the Auto Neg Enable bit and
* the Auto Neg Restart bit in the PHY control register.
*/
- if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
+ if(ret_val)
return ret_val;
phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
- if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data)))
+ ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
+ if(ret_val)
return ret_val;
/* Does the user want to wait for Auto-Neg to complete here, or
* check at a later time (for example, callback routine).
*/
if(hw->wait_autoneg_complete) {
- if((ret_val = e1000_wait_autoneg(hw))) {
+ ret_val = e1000_wait_autoneg(hw);
+ if(ret_val) {
DEBUGOUT("Error while waiting for autoneg to complete\n");
return ret_val;
}
@@ -1152,7 +1192,8 @@
hw->get_link_status = TRUE;
} else {
DEBUGOUT("Forcing speed and duplex\n");
- if((ret_val = e1000_phy_force_speed_duplex(hw))) {
+ ret_val = e1000_phy_force_speed_duplex(hw);
+ if(ret_val) {
DEBUGOUT("Error Forcing Speed and Duplex\n");
return ret_val;
}
@@ -1163,9 +1204,11 @@
* valid.
*/
for(i = 0; i < 10; i++) {
- if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+ if(ret_val)
return ret_val;
- if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+ if(ret_val)
return ret_val;
if(phy_data & MII_SR_LINK_STATUS) {
@@ -1180,19 +1223,22 @@
if(hw->mac_type >= e1000_82544) {
e1000_config_collision_dist(hw);
} else {
- if((ret_val = e1000_config_mac_to_phy(hw))) {
+ ret_val = e1000_config_mac_to_phy(hw);
+ if(ret_val) {
DEBUGOUT("Error configuring MAC to PHY settings\n");
return ret_val;
}
}
- if((ret_val = e1000_config_fc_after_link_up(hw))) {
+ ret_val = e1000_config_fc_after_link_up(hw);
+ if(ret_val) {
DEBUGOUT("Error Configuring Flow Control\n");
return ret_val;
}
DEBUGOUT("Valid link established!!!\n");
if(hw->phy_type == e1000_phy_igp) {
- if((ret_val = e1000_config_dsp_after_link_change(hw, TRUE))) {
+ ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
+ if(ret_val) {
DEBUGOUT("Error Configuring DSP after link up\n");
return ret_val;
}
@@ -1222,12 +1268,13 @@
DEBUGFUNC("e1000_phy_setup_autoneg");
/* Read the MII Auto-Neg Advertisement Register (Address 4). */
- if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
- &mii_autoneg_adv_reg)))
+ ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
+ if(ret_val)
return ret_val;
/* Read the MII 1000Base-T Control Register (Address 9). */
- if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg)))
+ ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
+ if(ret_val)
return ret_val;
/* Need to parse both autoneg_advertised and fc and set up
@@ -1334,13 +1381,14 @@
return -E1000_ERR_CONFIG;
}
- if((ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV,
- mii_autoneg_adv_reg)))
+ ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
+ if(ret_val)
return ret_val;
DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
- if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg)))
+ ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
+ if(ret_val)
return ret_val;
return E1000_SUCCESS;
@@ -1379,7 +1427,8 @@
ctrl &= ~E1000_CTRL_ASDE;
/* Read the MII Control Register. */
- if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg)))
+ ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
+ if(ret_val)
return ret_val;
/* We need to disable autoneg in order to force link and duplex. */
@@ -1426,16 +1475,16 @@
E1000_WRITE_REG(hw, CTRL, ctrl);
if (hw->phy_type == e1000_phy_m88) {
- if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
- &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
+ if(ret_val)
return ret_val;
/* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
* forced whenever speed are duplex are forced.
*/
phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
- if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
- phy_data)))
+ ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
+ if(ret_val)
return ret_val;
DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
@@ -1446,20 +1495,21 @@
/* Clear Auto-Crossover to force MDI manually. IGP requires MDI
* forced whenever speed or duplex are forced.
*/
- if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
- &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
+ if(ret_val)
return ret_val;
phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
- if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
- phy_data)))
+ ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
+ if(ret_val)
return ret_val;
}
/* Write back the modified PHY MII control register. */
- if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg)))
+ ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
+ if(ret_val)
return ret_val;
udelay(1);
@@ -1481,10 +1531,12 @@
/* Read the MII Status Register and wait for Auto-Neg Complete bit
* to be set.
*/
- if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
+ ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+ if(ret_val)
return ret_val;
- if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
+ ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+ if(ret_val)
return ret_val;
if(mii_status_reg & MII_SR_LINK_STATUS) break;
@@ -1492,7 +1544,8 @@
}
if((i == 0) && (hw->phy_type == e1000_phy_m88)) {
/* We didn't get link. Reset the DSP and wait again for link. */
- if((ret_val = e1000_phy_reset_dsp(hw))) {
+ ret_val = e1000_phy_reset_dsp(hw);
+ if(ret_val) {
DEBUGOUT("Error Resetting PHY DSP\n");
return ret_val;
}
@@ -1504,10 +1557,12 @@
/* Read the MII Status Register and wait for Auto-Neg Complete bit
* to be set.
*/
- if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
+ ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+ if(ret_val)
return ret_val;
- if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
+ ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+ if(ret_val)
return ret_val;
}
}
@@ -1517,46 +1572,26 @@
* Extended PHY Specific Control Register to 25MHz clock. This value
* defaults back to a 2.5MHz clock when the PHY is reset.
*/
- if((ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
- &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
+ if(ret_val)
return ret_val;
phy_data |= M88E1000_EPSCR_TX_CLK_25;
- if((ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
- phy_data)))
+ ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
+ if(ret_val)
return ret_val;
/* In addition, because of the s/w reset above, we need to enable CRS on
* TX. This must be set for both full and half duplex operation.
*/
- if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
- &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
+ if(ret_val)
return ret_val;
phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
- if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
- phy_data)))
+ ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
+ if(ret_val)
return ret_val;
-
- /* Polarity reversal workaround for forced 10F/10H links. */
- if(hw->mac_type <= e1000_82544 &&
- (hw->forced_speed_duplex == e1000_10_full ||
- hw->forced_speed_duplex == e1000_10_half)) {
- if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
- 0x0019)))
- return ret_val;
- if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL,
- 0x8F0F)))
- return ret_val;
- /* IEEE requirement is 150ms */
- msec_delay(200);
- if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
- 0x0019)))
- return ret_val;
- if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL,
- 0x8F00)))
- return ret_val;
- }
}
return E1000_SUCCESS;
}
@@ -1614,8 +1649,9 @@
* registers depending on negotiated values.
*/
if (hw->phy_type == e1000_phy_igp) {
- if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
- &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
+ &phy_data);
+ if(ret_val)
return ret_val;
if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD;
@@ -1633,8 +1669,9 @@
IGP01E1000_PSSR_SPEED_100MBPS)
ctrl |= E1000_CTRL_SPD_100;
} else {
- if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
- &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
+ &phy_data);
+ if(ret_val)
return ret_val;
if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD;
@@ -1752,7 +1789,8 @@
if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed)) ||
((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
- if((ret_val = e1000_force_mac_fc(hw))) {
+ ret_val = e1000_force_mac_fc(hw);
+ if(ret_val) {
DEBUGOUT("Error forcing flow control settings\n");
return ret_val;
}
@@ -1768,9 +1806,11 @@
* has completed. We read this twice because this reg has
* some "sticky" (latched) bits.
*/
- if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
+ ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+ if(ret_val)
return ret_val;
- if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
+ ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+ if(ret_val)
return ret_val;
if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
@@ -1780,11 +1820,13 @@
* Register (Address 5) to determine how flow control was
* negotiated.
*/
- if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
- &mii_nway_adv_reg)))
+ ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
+ &mii_nway_adv_reg);
+ if(ret_val)
return ret_val;
- if((ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
- &mii_nway_lp_ability_reg)))
+ ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
+ &mii_nway_lp_ability_reg);
+ if(ret_val)
return ret_val;
/* Two bits in the Auto Negotiation Advertisement Register
@@ -1901,7 +1943,8 @@
* negotiated to HALF DUPLEX, flow control should not be
* enabled per IEEE 802.3 spec.
*/
- if((ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex))) {
+ ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
+ if(ret_val) {
DEBUGOUT("Error getting link speed and duplex\n");
return ret_val;
}
@@ -1912,7 +1955,8 @@
/* Now we call a subroutine to actually force the MAC
* controller to use the correct flow control settings.
*/
- if((ret_val = e1000_force_mac_fc(hw))) {
+ ret_val = e1000_force_mac_fc(hw);
+ if(ret_val) {
DEBUGOUT("Error forcing flow control settings\n");
return ret_val;
}
@@ -1933,7 +1977,7 @@
int32_t
e1000_check_for_link(struct e1000_hw *hw)
{
- uint32_t rxcw;
+ uint32_t rxcw = 0;
uint32_t ctrl;
uint32_t status;
uint32_t rctl;
@@ -1943,16 +1987,23 @@
DEBUGFUNC("e1000_check_for_link");
+ ctrl = E1000_READ_REG(hw, CTRL);
+ status = E1000_READ_REG(hw, STATUS);
+
/* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
* set when the optics detect a signal. On older adapters, it will be
* cleared when there is a signal. This applies to fiber media only.
*/
- if(hw->media_type == e1000_media_type_fiber)
- signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
+ if((hw->media_type == e1000_media_type_fiber) ||
+ (hw->media_type == e1000_media_type_internal_serdes)) {
+ rxcw = E1000_READ_REG(hw, RXCW);
- ctrl = E1000_READ_REG(hw, CTRL);
- status = E1000_READ_REG(hw, STATUS);
- rxcw = E1000_READ_REG(hw, RXCW);
+ if(hw->media_type == e1000_media_type_fiber) {
+ signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
+ if(status & E1000_STATUS_LU)
+ hw->get_link_status = FALSE;
+ }
+ }
/* If we have a copper PHY then we only want to go out to the PHY
* registers to see if Auto-Neg has completed and/or if our link
@@ -1966,9 +2017,11 @@
* of the PHY.
* Read the register twice since the link bit is sticky.
*/
- if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+ if(ret_val)
return ret_val;
- if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+ if(ret_val)
return ret_val;
if(phy_data & MII_SR_LINK_STATUS) {
@@ -2002,7 +2055,8 @@
if(hw->mac_type >= e1000_82544)
e1000_config_collision_dist(hw);
else {
- if((ret_val = e1000_config_mac_to_phy(hw))) {
+ ret_val = e1000_config_mac_to_phy(hw);
+ if(ret_val) {
DEBUGOUT("Error configuring MAC to PHY settings\n");
return ret_val;
}
@@ -2012,7 +2066,8 @@
* need to restore the desired flow control settings because we may
* have had to re-autoneg with a different link partner.
*/
- if((ret_val = e1000_config_fc_after_link_up(hw))) {
+ ret_val = e1000_config_fc_after_link_up(hw);
+ if(ret_val) {
DEBUGOUT("Error configuring flow control\n");
return ret_val;
}
@@ -2061,8 +2116,8 @@
* in. The autoneg_failed flag does this.
*/
else if((((hw->media_type == e1000_media_type_fiber) &&
- ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
- (hw->media_type == e1000_media_type_internal_serdes)) &&
+ ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
+ (hw->media_type == e1000_media_type_internal_serdes)) &&
(!(status & E1000_STATUS_LU)) &&
(!(rxcw & E1000_RXCW_C))) {
if(hw->autoneg_failed == 0) {
@@ -2080,7 +2135,8 @@
E1000_WRITE_REG(hw, CTRL, ctrl);
/* Configure Flow Control after forcing link up. */
- if((ret_val = e1000_config_fc_after_link_up(hw))) {
+ ret_val = e1000_config_fc_after_link_up(hw);
+ if(ret_val) {
DEBUGOUT("Error configuring flow control\n");
return ret_val;
}
@@ -2092,8 +2148,7 @@
*/
else if(((hw->media_type == e1000_media_type_fiber) ||
(hw->media_type == e1000_media_type_internal_serdes)) &&
- (ctrl & E1000_CTRL_SLU) &&
- (rxcw & E1000_RXCW_C)) {
+ (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
E1000_WRITE_REG(hw, TXCW, hw->txcw);
E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
@@ -2173,13 +2228,15 @@
* match the duplex in the link partner's capabilities.
*/
if(hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
- if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
+ if(ret_val)
return ret_val;
if(!(phy_data & NWAY_ER_LP_NWAY_CAPS))
*duplex = HALF_DUPLEX;
else {
- if((ret_val == e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
+ if(ret_val)
return ret_val;
if((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
(*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
@@ -2210,9 +2267,11 @@
/* Read the MII Status Register and wait for Auto-Neg
* Complete bit to be set.
*/
- if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+ if(ret_val)
return ret_val;
- if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+ if(ret_val)
return ret_val;
if(phy_data & MII_SR_AUTONEG_COMPLETE) {
return E1000_SUCCESS;
@@ -2377,8 +2436,9 @@
if(hw->phy_type == e1000_phy_igp &&
(reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
- if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
- (uint16_t)reg_addr)))
+ ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
+ (uint16_t)reg_addr);
+ if(ret_val)
return ret_val;
}
@@ -2480,8 +2540,9 @@
if(hw->phy_type == e1000_phy_igp &&
(reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
- if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
- (uint16_t)reg_addr)))
+ ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
+ (uint16_t)reg_addr);
+ if(ret_val)
return ret_val;
}
@@ -2620,11 +2681,13 @@
DEBUGFUNC("e1000_phy_reset");
if(hw->mac_type != e1000_82541_rev_2) {
- if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
+ if(ret_val)
return ret_val;
phy_data |= MII_CR_RESET;
- if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data)))
+ ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
+ if(ret_val)
return ret_val;
udelay(1);
@@ -2651,12 +2714,14 @@
DEBUGFUNC("e1000_detect_gig_phy");
/* Read the PHY ID Registers to identify which PHY is onboard. */
- if((ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high)))
+ ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
+ if(ret_val)
return ret_val;
hw->phy_id = (uint32_t) (phy_id_high << 16);
udelay(20);
- if((ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low)))
+ ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
+ if(ret_val)
return ret_val;
hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
@@ -2708,9 +2773,12 @@
DEBUGFUNC("e1000_phy_reset_dsp");
do {
- if((ret_val = e1000_write_phy_reg(hw, 29, 0x001d))) break;
- if((ret_val = e1000_write_phy_reg(hw, 30, 0x00c1))) break;
- if((ret_val = e1000_write_phy_reg(hw, 30, 0x0000))) break;
+ ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
+ if(ret_val) break;
+ ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
+ if(ret_val) break;
+ ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
+ if(ret_val) break;
ret_val = E1000_SUCCESS;
} while(0);
@@ -2743,13 +2811,14 @@
phy_info->polarity_correction = e1000_polarity_reversal_enabled;
/* Check polarity status */
- if((ret_val = e1000_check_polarity(hw, &polarity)))
+ ret_val = e1000_check_polarity(hw, &polarity);
+ if(ret_val)
return ret_val;
phy_info->cable_polarity = polarity;
- if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
- &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
+ if(ret_val)
return ret_val;
phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >>
@@ -2758,7 +2827,8 @@
if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
IGP01E1000_PSSR_SPEED_1000MBPS) {
/* Local/Remote Receiver Information are only valid at 1000 Mbps */
- if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
+ if(ret_val)
return ret_val;
phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
@@ -2767,7 +2837,8 @@
SR_1000T_REMOTE_RX_STATUS_SHIFT;
/* Get cable length */
- if((ret_val = e1000_get_cable_length(hw, &min_length, &max_length)))
+ ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
+ if(ret_val)
return ret_val;
/* transalte to old method */
@@ -2807,7 +2878,8 @@
* and it stored in the hw->speed_downgraded parameter. */
phy_info->downshift = hw->speed_downgraded;
- if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
+ if(ret_val)
return ret_val;
phy_info->extended_10bt_distance =
@@ -2818,12 +2890,14 @@
M88E1000_PSCR_POLARITY_REVERSAL_SHIFT;
/* Check polarity status */
- if((ret_val = e1000_check_polarity(hw, &polarity)))
+ ret_val = e1000_check_polarity(hw, &polarity);
+ if(ret_val)
return ret_val;
phy_info->cable_polarity = polarity;
- if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
+ if(ret_val)
return ret_val;
phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
@@ -2836,7 +2910,8 @@
phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
M88E1000_PSSR_CABLE_LENGTH_SHIFT);
- if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
+ if(ret_val)
return ret_val;
phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
@@ -2878,10 +2953,12 @@
return -E1000_ERR_CONFIG;
}
- if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+ if(ret_val)
return ret_val;
- if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+ if(ret_val)
return ret_val;
if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
@@ -3344,6 +3421,7 @@
udelay(5);
retry_count += 5;
+ e1000_standby_eeprom(hw);
} while(retry_count < EEPROM_MAX_RETRY_SPI);
/* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
@@ -4112,12 +4190,14 @@
case e1000_82541_rev_2:
case e1000_82547_rev_2:
/* Turn off PHY Smart Power Down (if enabled) */
- if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
- &hw->phy_spd_default)))
- return ret_val;
- if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
- (uint16_t)(hw->phy_spd_default &
- ~IGP01E1000_GMII_SPD))))
+ ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
+ &hw->phy_spd_default);
+ if(ret_val)
+ return ret_val;
+ ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
+ (uint16_t)(hw->phy_spd_default &
+ ~IGP01E1000_GMII_SPD));
+ if(ret_val)
return ret_val;
/* Fall Through */
default:
@@ -4164,8 +4244,9 @@
case e1000_82541_rev_2:
case e1000_82547_rev_2:
/* Turn on PHY Smart Power Down (if previously enabled) */
- if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
- hw->phy_spd_default)))
+ ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
+ hw->phy_spd_default);
+ if(ret_val)
return ret_val;
/* Fall Through */
default:
@@ -4612,8 +4693,9 @@
/* Use old method for Phy older than IGP */
if(hw->phy_type == e1000_phy_m88) {
- if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
- &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
+ &phy_data);
+ if(ret_val)
return ret_val;
/* Convert the enum value to ranged values */
@@ -4652,7 +4734,8 @@
/* Read the AGC registers for all channels */
for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
- if((ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
+ if(ret_val)
return ret_val;
cur_agc = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
@@ -4719,15 +4802,17 @@
if(hw->phy_type == e1000_phy_m88) {
/* return the Polarity bit in the Status register. */
- if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
- &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
+ &phy_data);
+ if(ret_val)
return ret_val;
*polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
M88E1000_PSSR_REV_POLARITY_SHIFT;
} else if(hw->phy_type == e1000_phy_igp) {
/* Read the Status register to check the speed */
- if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
- &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
+ &phy_data);
+ if(ret_val)
return ret_val;
/* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
@@ -4736,8 +4821,9 @@
IGP01E1000_PSSR_SPEED_1000MBPS) {
/* Read the GIG initialization PCS register (0x00B4) */
- if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
- &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
+ &phy_data);
+ if(ret_val)
return ret_val;
/* Check the polarity bits */
@@ -4775,15 +4861,17 @@
DEBUGFUNC("e1000_check_downshift");
if(hw->phy_type == e1000_phy_igp) {
- if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
- &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
+ &phy_data);
+ if(ret_val)
return ret_val;
hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
}
else if(hw->phy_type == e1000_phy_m88) {
- if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
- &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
+ &phy_data);
+ if(ret_val)
return ret_val;
hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
@@ -4823,7 +4911,8 @@
return E1000_SUCCESS;
if(link_up) {
- if((ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex))) {
+ ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
+ if(ret_val) {
DEBUGOUT("Error getting link speed and duplex\n");
return ret_val;
}
@@ -4836,14 +4925,16 @@
min_length >= e1000_igp_cable_length_50) {
for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
- if((ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
- &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
+ &phy_data);
+ if(ret_val)
return ret_val;
phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
- if((ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
- phy_data)))
+ ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
+ phy_data);
+ if(ret_val)
return ret_val;
}
hw->dsp_config_state = e1000_dsp_config_activated;
@@ -4856,23 +4947,26 @@
uint32_t idle_errs = 0;
/* clear previous idle error counts */
- if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
- &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
+ &phy_data);
+ if(ret_val)
return ret_val;
for(i = 0; i < ffe_idle_err_timeout; i++) {
udelay(1000);
- if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
- &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
+ &phy_data);
+ if(ret_val)
return ret_val;
idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
if(idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
hw->ffe_config_state = e1000_ffe_config_active;
- if((ret_val = e1000_write_phy_reg(hw,
+ ret_val = e1000_write_phy_reg(hw,
IGP01E1000_PHY_DSP_FFE,
- IGP01E1000_PHY_DSP_FFE_CM_CP)))
+ IGP01E1000_PHY_DSP_FFE_CM_CP);
+ if(ret_val)
return ret_val;
break;
}
@@ -4884,43 +4978,87 @@
}
} else {
if(hw->dsp_config_state == e1000_dsp_config_activated) {
- if((ret_val = e1000_write_phy_reg(hw, 0x0000,
- IGP01E1000_IEEE_FORCE_GIGA)))
+ ret_val = e1000_write_phy_reg(hw, 0x0000,
+ IGP01E1000_IEEE_FORCE_GIGA);
+ if(ret_val)
return ret_val;
for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
- if((ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
- &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
+ if(ret_val)
return ret_val;
phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
- if((ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i],
- phy_data)))
+ ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
+ if(ret_val)
return ret_val;
}
- if((ret_val = e1000_write_phy_reg(hw, 0x0000,
- IGP01E1000_IEEE_RESTART_AUTONEG)))
+ ret_val = e1000_write_phy_reg(hw, 0x0000,
+ IGP01E1000_IEEE_RESTART_AUTONEG);
+ if(ret_val)
return ret_val;
hw->dsp_config_state = e1000_dsp_config_enabled;
}
if(hw->ffe_config_state == e1000_ffe_config_active) {
- if((ret_val = e1000_write_phy_reg(hw, 0x0000,
- IGP01E1000_IEEE_FORCE_GIGA)))
+ ret_val = e1000_write_phy_reg(hw, 0x0000,
+ IGP01E1000_IEEE_FORCE_GIGA);
+ if(ret_val)
+ return ret_val;
+ ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
+ IGP01E1000_PHY_DSP_FFE_DEFAULT);
+ if(ret_val)
return ret_val;
- if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
- IGP01E1000_PHY_DSP_FFE_DEFAULT)))
+
+ ret_val = e1000_write_phy_reg(hw, 0x0000,
+ IGP01E1000_IEEE_RESTART_AUTONEG);
+ if(ret_val)
return ret_val;
+ hw->ffe_config_state = e1000_ffe_config_enabled;
+ }
+ }
+ return E1000_SUCCESS;
+}
+
+/*****************************************************************************
+ * Set PHY to class A mode
+ * Assumes the following operations will follow to enable the new class mode.
+ * 1. Do a PHY soft reset
+ * 2. Restart auto-negotiation or force link.
+ *
+ * hw - Struct containing variables accessed by shared code
+ ****************************************************************************/
+static int32_t
+e1000_set_phy_mode(struct e1000_hw *hw)
+{
+ int32_t ret_val;
+ uint16_t eeprom_data;
+
+ DEBUGFUNC("e1000_set_phy_mode");
+
+ if((hw->mac_type == e1000_82545_rev_3) &&
+ (hw->media_type == e1000_media_type_copper)) {
+ ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
+ if(ret_val) {
+ return ret_val;
+ }
- if((ret_val = e1000_write_phy_reg(hw, 0x0000,
- IGP01E1000_IEEE_RESTART_AUTONEG)))
+ if((eeprom_data != EEPROM_RESERVED_WORD) &&
+ (eeprom_data & EEPROM_PHY_CLASS_A)) {
+ ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
+ if(ret_val)
return ret_val;
- hw->ffe_config_state = e1000_ffe_config_enabled;
+ ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
+ if(ret_val)
+ return ret_val;
+
+ hw->phy_reset_disable = FALSE;
}
}
+
return E1000_SUCCESS;
}
@@ -4953,25 +5091,27 @@
/* During driver activity LPLU should not be used or it will attain link
* from the lowest speeds starting from 10Mbps. The capability is used for
* Dx transitions and states */
- if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
+ if(ret_val)
return ret_val;
if(!active) {
phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
- if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data)))
+ ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
+ if(ret_val)
return ret_val;
/* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
* Dx states where the power conservation is most important. During
* driver activity we should enable SmartSpeed, so performance is
* maintained. */
- if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
- &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
+ if(ret_val)
return ret_val;
phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
- if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
- phy_data)))
+ ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
+ if(ret_val)
return ret_val;
} else if((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
@@ -4979,17 +5119,18 @@
(hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
phy_data |= IGP01E1000_GMII_FLEX_SPD;
- if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data)))
+ ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
+ if(ret_val)
return ret_val;
/* When LPLU is enabled we should disable SmartSpeed */
- if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
- &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
+ if(ret_val)
return ret_val;
phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
- if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
- phy_data)))
+ ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
+ if(ret_val)
return ret_val;
}
@@ -5020,36 +5161,66 @@
/* Set PHY register 30, page 5, bit 8 to 0 */
- if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
- &default_page)))
+ ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
+ if(ret_val)
return ret_val;
- if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005)))
+ ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
+ if(ret_val)
return ret_val;
- if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
+ if(ret_val)
return ret_val;
phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
- if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data)))
+ ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
+ if(ret_val)
return ret_val;
/* Set PHY register 30, page 4, bit 11 to 1 */
- if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004)))
+ ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
+ if(ret_val)
return ret_val;
- if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data)))
+ ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
+ if(ret_val)
return ret_val;
phy_data |= M88E1000_PHY_VCO_REG_BIT11;
- if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data)))
+ ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
+ if(ret_val)
return ret_val;
- if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
- default_page)))
+ ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
+ if(ret_val)
return ret_val;
return E1000_SUCCESS;
}
+/******************************************************************************
+ * Verifies the hardware needs to allow ARPs to be processed by the host
+ *
+ * hw - Struct containing variables accessed by shared code
+ *
+ * returns: - TRUE/FALSE
+ *
+ *****************************************************************************/
+uint32_t
+e1000_enable_mng_pass_thru(struct e1000_hw *hw)
+{
+ uint32_t manc;
+
+ if (hw->asf_firmware_present) {
+ manc = E1000_READ_REG(hw, MANC);
+
+ if (!(manc & E1000_MANC_RCV_TCO_EN) ||
+ !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
+ return FALSE;
+ if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
+ return TRUE;
+ }
+ return FALSE;
+}
FUNET's LINUX-ADM group, linux-adm@nic.funet.fi
TCL-scripts by Sam Shen (who was at: slshen@lbl.gov)