patch-2.4.7 linux/drivers/net/sk98lin/h/skgehw.h
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- Lines: 1602
- Date:
Wed Jul 4 11:50:39 2001
- Orig file:
v2.4.6/linux/drivers/net/sk98lin/h/skgehw.h
- Orig date:
Tue Mar 20 12:04:59 2001
diff -u --recursive --new-file v2.4.6/linux/drivers/net/sk98lin/h/skgehw.h linux/drivers/net/sk98lin/h/skgehw.h
@@ -2,8 +2,8 @@
*
* Name: skgehw.h
* Project: GEnesis, PCI Gigabit Ethernet Adapter
- * Version: $Revision: 1.35 $
- * Date: $Date: 2000/05/19 10:17:13 $
+ * Version: $Revision: 1.36 $
+ * Date: $Date: 2000/11/09 12:32:49 $
* Purpose: Defines and Macros for the Gigabit Ethernet Adapter Product
* Family
*
@@ -11,8 +11,7 @@
/******************************************************************************
*
- * (C)Copyright 1998,1999 SysKonnect,
- * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ * (C)Copyright 1998-2000 SysKonnect GmbH.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -27,6 +26,9 @@
*
* History:
* $Log: skgehw.h,v $
+ * Revision 1.36 2000/11/09 12:32:49 rassmann
+ * Renamed variables.
+ *
* Revision 1.35 2000/05/19 10:17:13 cgoos
* Added inactivity check in PHY_READ (in DEBUG mode only).
*
@@ -180,27 +182,27 @@
*/
#define PCI_VENDOR_ID 0x00 /* 16 bit Vendor ID */
#define PCI_DEVICE_ID 0x02 /* 16 bit Device ID */
-#define PCI_COMMAND 0x04 /* 16 bit Command */
-#define PCI_STATUS 0x06 /* 16 bit Status */
-#define PCI_REV_ID 0x08 /* 8 bit Revision ID */
+#define PCI_COMMAND 0x04 /* 16 bit Command */
+#define PCI_STATUS 0x06 /* 16 bit Status */
+#define PCI_REV_ID 0x08 /* 8 bit Revision ID */
#define PCI_CLASS_CODE 0x09 /* 24 bit Class Code */
#define PCI_CACHE_LSZ 0x0c /* 8 bit Cache Line Size */
-#define PCI_LAT_TIM 0x0d /* 8 bit Latency Timer */
+#define PCI_LAT_TIM 0x0d /* 8 bit Latency Timer */
#define PCI_HEADER_T 0x0e /* 8 bit Header Type */
-#define PCI_BIST 0x0f /* 8 bit Built-in selftest */
+#define PCI_BIST 0x0f /* 8 bit Built-in selftest */
#define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */
#define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */
/* Byte 18..2b: reserved */
-#define PCI_SUB_VID 0x2c /* 16 bit Subsystem Vendor ID */
-#define PCI_SUB_ID 0x2e /* 16 bit Subsystem ID */
+#define PCI_SUB_VID 0x2c /* 16 bit Subsystem Vendor ID */
+#define PCI_SUB_ID 0x2e /* 16 bit Subsystem ID */
#define PCI_BASE_ROM 0x30 /* 32 bit Expansion ROM Base Address */
/* Byte 34..33: reserved */
-#define PCI_CAP_PTR 0x34 /* 8 bit Capabilities Ptr */
+#define PCI_CAP_PTR 0x34 /* 8 bit Capabilities Ptr */
/* Byte 35..3b: reserved */
#define PCI_IRQ_LINE 0x3c /* 8 bit Interrupt Line */
-#define PCI_IRQ_PIN 0x3d /* 8 bit Interrupt Pin */
-#define PCI_MIN_GNT 0x3e /* 8 bit Min_Gnt */
-#define PCI_MAX_LAT 0x3f /* 8 bit Max_Lat */
+#define PCI_IRQ_PIN 0x3d /* 8 bit Interrupt Pin */
+#define PCI_MIN_GNT 0x3e /* 8 bit Min_Gnt */
+#define PCI_MAX_LAT 0x3f /* 8 bit Max_Lat */
/* Device Dependent Region */
#define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */
#define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */
@@ -233,34 +235,34 @@
/* PCI_DEVICE_ID 16 bit Device ID */
/* Values for Vendor ID and Device ID shall be patched into the code */
/* PCI_COMMAND 16 bit Command */
- /* Bit 15..10: reserved */
-#define PCI_FBTEN (1<<9) /* Bit 9: Fast Back-To-Back enable */
-#define PCI_SERREN (1<<8) /* Bit 8: SERR enable */
-#define PCI_ADSTEP (1<<7) /* Bit 7: Address Stepping */
-#define PCI_PERREN (1<<6) /* Bit 6: Parity Report Response enable */
+ /* Bit 15..10: reserved */
+#define PCI_FBTEN (1<<9) /* Bit 9: Fast Back-To-Back enable */
+#define PCI_SERREN (1<<8) /* Bit 8: SERR enable */
+#define PCI_ADSTEP (1<<7) /* Bit 7: Address Stepping */
+#define PCI_PERREN (1<<6) /* Bit 6: Parity Report Response enable */
#define PCI_VGA_SNOOP (1<<5) /* Bit 5: VGA palette snoop */
-#define PCI_MWIEN (1<<4) /* Bit 4: Memory write an inv cycl ena */
-#define PCI_SCYCEN (1<<3) /* Bit 3: Special Cycle enable */
-#define PCI_BMEN (1<<2) /* Bit 2: Bus Master enable */
-#define PCI_MEMEN (1<<1) /* Bit 1: Memory Space Access enable */
-#define PCI_IOEN (1<<0) /* Bit 0: IO Space Access enable */
+#define PCI_MWIEN (1<<4) /* Bit 4: Memory write an inv cycl ena */
+#define PCI_SCYCEN (1<<3) /* Bit 3: Special Cycle enable */
+#define PCI_BMEN (1<<2) /* Bit 2: Bus Master enable */
+#define PCI_MEMEN (1<<1) /* Bit 1: Memory Space Access enable */
+#define PCI_IOEN (1<<0) /* Bit 0: IO Space Access enable */
/* PCI_STATUS 16 bit Status */
-#define PCI_PERR (1<<15) /* Bit 15: Parity Error */
-#define PCI_SERR (1<<14) /* Bit 14: Signaled SERR */
-#define PCI_RMABORT (1<<13) /* Bit 13: Received Master Abort */
-#define PCI_RTABORT (1<<12) /* Bit 12: Received Target Abort */
- /* Bit 11: reserved */
-#define PCI_DEVSEL (3<<9) /* Bit 10..9: DEVSEL Timing */
+#define PCI_PERR (1<<15) /* Bit 15: Parity Error */
+#define PCI_SERR (1<<14) /* Bit 14: Signaled SERR */
+#define PCI_RMABORT (1<<13) /* Bit 13: Received Master Abort */
+#define PCI_RTABORT (1<<12) /* Bit 12: Received Target Abort */
+ /* Bit 11: reserved */
+#define PCI_DEVSEL (3<<9) /* Bit 10..9: DEVSEL Timing */
#define PCI_DEV_FAST (0<<9) /* fast */
#define PCI_DEV_MEDIUM (1<<9) /* medium */
#define PCI_DEV_SLOW (2<<9) /* slow */
#define PCI_DATAPERR (1<<8) /* Bit 8: DATA Parity error detected */
-#define PCI_FB2BCAP (1<<7) /* Bit 7: Fast Back-to-Back Capability */
-#define PCI_UDF (1<<6) /* Bit 6: User Defined Features */
+#define PCI_FB2BCAP (1<<7) /* Bit 7: Fast Back-to-Back Capability */
+#define PCI_UDF (1<<6) /* Bit 6: User Defined Features */
#define PCI_66MHZCAP (1<<5) /* Bit 5: 66 MHz PCI bus clock capable */
-#define PCI_NEWCAP (1<<4) /* Bit 4: New cap. list implemented */
- /* Bit 3..0: reserved */
+#define PCI_NEWCAP (1<<4) /* Bit 4: New cap. list implemented */
+ /* Bit 3..0: reserved */
#define PCI_ERRBITS (PCI_PERR | PCI_SERR | PCI_RMABORT | PCI_RTABORT |\
PCI_DATAPERR)
@@ -275,59 +277,59 @@
/* PCI_HEADER_T 8 bit Header Type */
#define PCI_HD_MF_DEV (1<<7) /* Bit 7: 0= single, 1= multi-func dev */
-#define PCI_HD_TYPE 0x7f /* Bit 6..0: Header Layout 0= normal */
+#define PCI_HD_TYPE 0x7f /* Bit 6..0: Header Layout 0= normal */
/* PCI_BIST 8 bit Built-in selftest */
/* Built-in Self test not supported (optional) */
/* PCI_BASE_1ST 32 bit 1st Base address */
-#define PCI_MEMSIZE 0x4000L /* use 16 kB Memory Base */
+#define PCI_MEMSIZE 0x4000L /* use 16 kB Memory Base */
#define PCI_MEMBASE_MSK 0xffffc000L /* Bit 31..14: Memory Base Address */
#define PCI_MEMSIZE_MSK 0x00003ff0L /* Bit 13.. 4: Memory Size Req. */
-#define PCI_PREFEN (1L<<3) /* Bit 3: Prefetchable */
-#define PCI_MEM_TYP (3L<<2) /* Bit 2.. 1: Memory Type */
+#define PCI_PREFEN (1L<<3) /* Bit 3: Prefetchable */
+#define PCI_MEM_TYP (3L<<2) /* Bit 2.. 1: Memory Type */
#define PCI_MEM32BIT (0L<<1) /* Base addr anywhere in 32 Bit range */
-#define PCI_MEM1M (1L<<1) /* Base addr below 1 MegaByte */
+#define PCI_MEM1M (1L<<1) /* Base addr below 1 MegaByte */
#define PCI_MEM64BIT (2L<<1) /* Base addr anywhere in 64 Bit range */
#define PCI_MEMSPACE (1L<<0) /* Bit 0: Memory Space Indic. */
/* PCI_BASE_2ND 32 bit 2nd Base address */
-#define PCI_IOBASE 0xffffff00L /* Bit 31..8: I/O Base address */
-#define PCI_IOSIZE 0x000000fcL /* Bit 7..2: I/O Size Requirements */
- /* Bit 1: reserved */
-#define PCI_IOSPACE (1L<<0) /* Bit 0: I/O Space Indicator */
+#define PCI_IOBASE 0xffffff00L /* Bit 31..8: I/O Base address */
+#define PCI_IOSIZE 0x000000fcL /* Bit 7..2: I/O Size Requirements */
+ /* Bit 1: reserved */
+#define PCI_IOSPACE (1L<<0) /* Bit 0: I/O Space Indicator */
/* PCI_BASE_ROM 32 bit Expansion ROM Base Address */
-#define PCI_ROMBASE (0xfffeL<<17) /* Bit 31..17: ROM BASE address (1st)*/
-#define PCI_ROMBASZ (0x1cL<<14) /* Bit 16..14: Treat as BASE or SIZE */
-#define PCI_ROMSIZE (0x38L<<11) /* Bit 13..11: ROM Size Requirements */
- /* Bit 10.. 1: reserved */
-#define PCI_ROMEN (0x1L<<0) /* Bit 0: Address Decode enable */
+#define PCI_ROMBASE (0xfffeL<<17) /* Bit 31..17: ROM BASE address (1st)*/
+#define PCI_ROMBASZ (0x1cL<<14) /* Bit 16..14: Treat as BASE or SIZE */
+#define PCI_ROMSIZE (0x38L<<11) /* Bit 13..11: ROM Size Requirements */
+ /* Bit 10.. 1: reserved */
+#define PCI_ROMEN (0x1L<<0) /* Bit 0: Address Decode enable */
/* Device Dependent Region */
/* PCI_OUR_REG_1 32 bit Our Register 1 */
- /* Bit 31..26: reserved */
-#define PCI_VIO (1L<<25) /* Bit 25: PCI IO Voltage, */
- /* 0 = 3.3V / 1 = 5V */
-#define PCI_EN_BOOT (1L<<24) /* Bit 24: Enable BOOT via ROM */
- /* 1 = Don't boot wth ROM*/
- /* 0 = Boot with ROM */
-#define PCI_EN_IO (1L<<23) /* Bit 23: Mapping to IO space */
+ /* Bit 31..26: reserved */
+#define PCI_VIO (1L<<25) /* Bit 25: PCI IO Voltage, */
+ /* 0 = 3.3V / 1 = 5V */
+#define PCI_EN_BOOT (1L<<24) /* Bit 24: Enable BOOT via ROM */
+ /* 1 = Don't boot wth ROM*/
+ /* 0 = Boot with ROM */
+#define PCI_EN_IO (1L<<23) /* Bit 23: Mapping to IO space */
#define PCI_EN_FPROM (1L<<22) /* Bit 22: FLASH mapped to mem? */
- /* 1 = Map Flash to Mem */
- /* 0 = Disable addr. dec*/
+ /* 1 = Map Flash to Mem */
+ /* 0 = Disable addr. dec*/
#define PCI_PAGESIZE (3L<<20) /* Bit 21..20: FLASH Page Size */
-#define PCI_PAGE_16 (0L<<20) /* 16 k pages */
+#define PCI_PAGE_16 (0L<<20) /* 16 k pages */
#define PCI_PAGE_32K (1L<<20) /* 32 k pages */
#define PCI_PAGE_64K (2L<<20) /* 64 k pages */
#define PCI_PAGE_128K (3L<<20) /* 128 k pages */
- /* Bit 19: reserved */
-#define PCI_PAGEREG (7L<<16) /* Bit 18..16: Page Register */
-#define PCI_NOTAR (1L<<15) /* Bit 15: No turnaround cycle */
+ /* Bit 19: reserved */
+#define PCI_PAGEREG (7L<<16) /* Bit 18..16: Page Register */
+#define PCI_NOTAR (1L<<15) /* Bit 15: No turnaround cycle */
#define PCI_FORCE_BE (1L<<14) /* Bit 14: Assert all BEs on MR */
-#define PCI_DIS_MRL (1L<<13) /* Bit 13: Disable Mem R Line */
-#define PCI_DIS_MRM (1L<<12) /* Bit 12: Disable Mem R multip */
-#define PCI_DIS_MWI (1L<<11) /* Bit 11: Disable Mem W & inv */
+#define PCI_DIS_MRL (1L<<13) /* Bit 13: Disable Mem R Line */
+#define PCI_DIS_MRM (1L<<12) /* Bit 12: Disable Mem R multip */
+#define PCI_DIS_MWI (1L<<11) /* Bit 11: Disable Mem W & inv */
#define PCI_DISC_CLS (1L<<10) /* Bit 10: Disc: cacheLsz bound */
#define PCI_BURST_DIS (1L<<9) /* Bit 9: Burst Disable */
#define PCI_DIS_PCI_CLK (1L<<8) /* Bit 8: Disable PCI clock driv*/
@@ -337,9 +339,9 @@
/* PCI_OUR_REG_2 32 bit Our Register 2 */
#define PCI_VPD_WR_THR (0xffL<<24) /* Bit 31..24: VPD Write Threshold */
-#define PCI_DEV_SEL (0x7fL<<17) /* Bit 23..17: EEPROM Device Select */
+#define PCI_DEV_SEL (0x7fL<<17) /* Bit 23..17: EEPROM Device Select */
#define PCI_VPD_ROM_SZ (7L<<14) /* Bit 16..14: VPD ROM Size */
- /* Bit 13..12: reserved */
+ /* Bit 13..12: reserved */
#define PCI_PATCH_DIR (0xfL<<8) /* Bit 11.. 8: Ext Patchs dir 3..0 */
#define PCI_PATCH_DIR_0 (1L<<8)
#define PCI_PATCH_DIR_1 (1L<<9)
@@ -352,27 +354,27 @@
#define PCI_EXT_PATCH_3 (1L<<7)
#define PCI_EN_DUMMY_RD (1L<<3) /* Bit 3: Enable Dummy Read */
#define PCI_REV_DESC (1L<<2) /* Bit 2: Reverse Desc. Bytes */
- /* Bit 1: reserved */
+ /* Bit 1: reserved */
#define PCI_USEDATA64 (1L<<0) /* Bit 0: Use 64Bit Data bus ext*/
/* Power Management Region */
/* PCI_PM_CAP_REG 16 bit Power Management Capabilities */
-#define PCI_PME_SUP (0x1f<<11) /* Bit 15..11: PM Manag. Event Sup */
+#define PCI_PME_SUP (0x1f<<11) /* Bit 15..11: PM Manag. Event Sup */
#define PCI_PM_D2_SUB (1<<10) /* Bit 10: D2 Support Bit */
#define PCI_PM_D1_SUB (1<<9) /* Bit 9: D1 Support Bit */
- /* Bit 8..6: reserved */
-#define PCI_PM_DSI (1<<5) /* Bit 5: Device Specific Init.*/
-#define PCI_PM_APS (1<<4) /* Bit 4: Auxialiary Power Src */
+ /* Bit 8..6: reserved */
+#define PCI_PM_DSI (1<<5) /* Bit 5: Device Specific Init.*/
+#define PCI_PM_APS (1<<4) /* Bit 4: Auxialiary Power Src */
#define PCI_PME_CLOCK (1<<3) /* Bit 3: PM Event Clock */
-#define PCI_PM_VER (7<<0) /* Bit 2..0: PM PCI Spec. version */
+#define PCI_PM_VER (7<<0) /* Bit 2..0: PM PCI Spec. version */
/* PCI_PM_CTL_STS 16 bit Power Manag. Control/Status */
#define PCI_PME_STATUS (1<<15) /* Bit 15: PGA doesn't sup. PME# */
#define PCI_PM_DAT_SCL (3<<13) /* Bit 14..13: dat reg Scaling factor*/
#define PCI_PM_DAT_SEL (0xf<<9) /* Bit 12.. 9: PM data selector field*/
-#define PCI_PME_EN (1<<8) /* Bit 8: PGA doesn't sup. PME# */
- /* Bit 7.. 2: reserved */
+#define PCI_PME_EN (1<<8) /* Bit 8: PGA doesn't sup. PME# */
+ /* Bit 7.. 2: reserved */
#define PCI_PM_STATE (3<<0) /* Bit 1.. 0: Power Management State*/
#define PCI_PM_STATE_D0 (0<<0) /* D0: Operational (default) */
#define PCI_PM_STATE_D1 (1<<0) /* D1: not supported */
@@ -388,22 +390,22 @@
* Control Register File:
* Bank 0
*/
-#define B0_RAP 0x0000 /* 8 bit Register Address Port */
+#define B0_RAP 0x0000 /* 8 bit Register Address Port */
/* 0x0001 - 0x0003: reserved */
-#define B0_CTST 0x0004 /* 16 bit Control/Status register */
-#define B0_LED 0x0006 /* 8 Bit LED register */
+#define B0_CTST 0x0004 /* 16 bit Control/Status register */
+#define B0_LED 0x0006 /* 8 Bit LED register */
/* 0x0007: reserved */
-#define B0_ISRC 0x0008 /* 32 bit Interrupt Source Register */
-#define B0_IMSK 0x000c /* 32 bit Interrupt Mask Register */
-#define B0_HWE_ISRC 0x0010 /* 32 bit HW Error Interrupt Src Reg */
-#define B0_HWE_IMSK 0x0014 /* 32 bit HW Error Interrupt Mask Reg */
-#define B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg */
+#define B0_ISRC 0x0008 /* 32 bit Interrupt Source Register */
+#define B0_IMSK 0x000c /* 32 bit Interrupt Mask Register */
+#define B0_HWE_ISRC 0x0010 /* 32 bit HW Error Interrupt Src Reg */
+#define B0_HWE_IMSK 0x0014 /* 32 bit HW Error Interrupt Mask Reg */
+#define B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg */
/* 0x001c: reserved */
/* B0 XMAC 1 registers */
-#define B0_XM1_IMSK 0x0020 /* 16 bit r/w XMAC 1 Interrupt Mask Register*/
+#define B0_XM1_IMSK 0x0020 /* 16 bit r/w XMAC 1 Interrupt Mask Register*/
/* 0x0022 - 0x0027 reserved */
-#define B0_XM1_ISRC 0x0028 /* 16 bit ro XMAC 1 Interrupt Status Reg */
+#define B0_XM1_ISRC 0x0028 /* 16 bit ro XMAC 1 Interrupt Status Reg */
/* 0x002a - 0x002f reserved */
#define B0_XM1_PHY_ADDR 0x0030 /* 16 bit r/w XMAC 1 PHY Address Register */
/* 0x0032 - 0x0033 reserved */
@@ -411,9 +413,9 @@
/* 0x0036 - 0x003f reserved */
/* B0 XMAC 2 registers */
-#define B0_XM2_IMSK 0x0040 /* 16 bit r/w XMAC 2 Interrupt Mask Register*/
+#define B0_XM2_IMSK 0x0040 /* 16 bit r/w XMAC 2 Interrupt Mask Register*/
/* 0x0042 - 0x0047 reserved */
-#define B0_XM2_ISRC 0x0048 /* 16 bit ro XMAC 2 Interrupt Status Reg */
+#define B0_XM2_ISRC 0x0048 /* 16 bit ro XMAC 2 Interrupt Status Reg */
/* 0x004a - 0x004f reserved */
#define B0_XM2_PHY_ADDR 0x0050 /* 16 bit r/w XMAC 2 PHY Address Register */
/* 0x0052 - 0x0053 reserved */
@@ -421,12 +423,12 @@
/* 0x0056 - 0x005f reserved */
/* BMU Control Status Registers */
-#define B0_R1_CSR 0x0060 /* 32 bit BMU Ctrl/Stat Rx Queue 1 */
-#define B0_R2_CSR 0x0064 /* 32 bit BMU Ctrl/Stat Rx Queue 2 */
-#define B0_XS1_CSR 0x0068 /* 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
-#define B0_XA1_CSR 0x006c /* 32 bit BMU Ctrl/Stat Async Tx Queue 1*/
-#define B0_XS2_CSR 0x0070 /* 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
-#define B0_XA2_CSR 0x0074 /* 32 bit BMU Ctrl/Stat Async Tx Queue 2*/
+#define B0_R1_CSR 0x0060 /* 32 bit BMU Ctrl/Stat Rx Queue 1 */
+#define B0_R2_CSR 0x0064 /* 32 bit BMU Ctrl/Stat Rx Queue 2 */
+#define B0_XS1_CSR 0x0068 /* 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
+#define B0_XA1_CSR 0x006c /* 32 bit BMU Ctrl/Stat Async Tx Queue 1*/
+#define B0_XS2_CSR 0x0070 /* 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
+#define B0_XA2_CSR 0x0074 /* 32 bit BMU Ctrl/Stat Async Tx Queue 2*/
/* x0078 - 0x007f reserved */
/*
@@ -440,34 +442,34 @@
*/
/* NA reg = 48 bit Network Address Register, 3x16 or 8x8 bit readable */
-#define B2_MAC_1 0x0100 /* NA reg MAC Address 1 */
+#define B2_MAC_1 0x0100 /* NA reg MAC Address 1 */
/* 0x0106 - 0x0107 reserved */
-#define B2_MAC_2 0x0108 /* NA reg MAC Address 2 */
+#define B2_MAC_2 0x0108 /* NA reg MAC Address 2 */
/* 0x010e - 0x010f reserved */
-#define B2_MAC_3 0x0110 /* NA reg MAC Address 3 */
+#define B2_MAC_3 0x0110 /* NA reg MAC Address 3 */
/* 0x0116 - 0x0117 reserved */
-#define B2_CONN_TYP 0x0118 /* 8 bit Connector type */
-#define B2_PMD_TYP 0x0119 /* 8 bit PMD type */
-#define B2_MAC_CFG 0x011a /* 8 bit MAC Configuration */
-#define B2_CHIP_REV 0x011b /* 8 bit Queen Chip Revision Number */
+#define B2_CONN_TYP 0x0118 /* 8 bit Connector type */
+#define B2_PMD_TYP 0x0119 /* 8 bit PMD type */
+#define B2_MAC_CFG 0x011a /* 8 bit MAC Configuration */
+#define B2_CHIP_REV 0x011b /* 8 bit Queen Chip Revision Number */
/* Eprom registers are currently of no use */
-#define B2_E_0 0x011c /* 8 bit EPROM Byte 0 */
-#define B2_E_1 0x011d /* 8 bit EPROM Byte 1 */
-#define B2_E_2 0x011e /* 8 bit EPROM Byte 2 */
-#define B2_E_3 0x011f /* 8 bit EPROM Byte 3 */
-#define B2_FAR 0x0120 /* 32 bit Flash-Prom Addr Reg/Cnt */
-#define B2_FDP 0x0124 /* 8 bit Flash-Prom Data Port */
+#define B2_E_0 0x011c /* 8 bit EPROM Byte 0 */
+#define B2_E_1 0x011d /* 8 bit EPROM Byte 1 */
+#define B2_E_2 0x011e /* 8 bit EPROM Byte 2 */
+#define B2_E_3 0x011f /* 8 bit EPROM Byte 3 */
+#define B2_FAR 0x0120 /* 32 bit Flash-Prom Addr Reg/Cnt */
+#define B2_FDP 0x0124 /* 8 bit Flash-Prom Data Port */
/* 0x0125 - 0x0127: reserved */
-#define B2_LD_CRTL 0x0128 /* 8 bit EPROM loader control register */
-#define B2_LD_TEST 0x0129 /* 8 bit EPROM loader test register */
+#define B2_LD_CRTL 0x0128 /* 8 bit EPROM loader control register */
+#define B2_LD_TEST 0x0129 /* 8 bit EPROM loader test register */
/* 0x012a - 0x012f: reserved */
-#define B2_TI_INI 0x0130 /* 32 bit Timer init value */
-#define B2_TI_VAL 0x0134 /* 32 bit Timer value */
-#define B2_TI_CRTL 0x0138 /* 8 bit Timer control */
-#define B2_TI_TEST 0x0139 /* 8 Bit Timer Test */
+#define B2_TI_INI 0x0130 /* 32 bit Timer init value */
+#define B2_TI_VAL 0x0134 /* 32 bit Timer value */
+#define B2_TI_CRTL 0x0138 /* 8 bit Timer control */
+#define B2_TI_TEST 0x0139 /* 8 Bit Timer Test */
/* 0x013a - 0x013f: reserved */
-#define B2_IRQM_INI 0x0140 /* 32 bit IRQ Moderation Timer Init Reg.*/
-#define B2_IRQM_VAL 0x0144 /* 32 bit IRQ Moderation Timer Value */
+#define B2_IRQM_INI 0x0140 /* 32 bit IRQ Moderation Timer Init Reg.*/
+#define B2_IRQM_VAL 0x0144 /* 32 bit IRQ Moderation Timer Value */
#define B2_IRQM_CTRL 0x0148 /* 8 bit IRQ Moderation Timer Control */
#define B2_IRQM_TEST 0x0149 /* 8 bit IRQ Moderation Timer Test */
#define B2_IRQM_MSK 0x014c /* 32 bit IRQ Moderation Mask */
@@ -476,22 +478,22 @@
#define B2_TST_CTRL1 0x0158 /* 8 bit Test Control Register 1 */
#define B2_TST_CTRL2 0x0159 /* 8 bit Test Control Register 2 */
/* 0x015a - 0x015b: reserved */
-#define B2_GP_IO 0x015c /* 32 bit General Purpose IO Register */
-#define B2_I2C_CTRL 0x0160 /* 32 bit I2C HW Control Register */
-#define B2_I2C_DATA 0x0164 /* 32 bit I2C HW Data Register */
-#define B2_I2C_IRQ 0x0168 /* 32 bit I2C HW IRQ Register */
-#define B2_I2C_SW 0x016c /* 32 bit I2C SW Port Register */
-#define B2_BSC_INI 0x0170 /* 32 bit Blink Source Counter Init Val */
-#define B2_BSC_VAL 0x0174 /* 32 bit Blink Source Counter Value */
-#define B2_BSC_CTRL 0x0178 /* 8 bit Blink Source Counter Control */
-#define B2_BSC_STAT 0x0179 /* 8 bit Blink Source Counter Status */
-#define B2_BSC_TST 0x017a /* 16 bit Blink Source Counter Test Reg */
+#define B2_GP_IO 0x015c /* 32 bit General Purpose IO Register */
+#define B2_I2C_CTRL 0x0160 /* 32 bit I2C HW Control Register */
+#define B2_I2C_DATA 0x0164 /* 32 bit I2C HW Data Register */
+#define B2_I2C_IRQ 0x0168 /* 32 bit I2C HW IRQ Register */
+#define B2_I2C_SW 0x016c /* 32 bit I2C SW Port Register */
+#define B2_BSC_INI 0x0170 /* 32 bit Blink Source Counter Init Val */
+#define B2_BSC_VAL 0x0174 /* 32 bit Blink Source Counter Value */
+#define B2_BSC_CTRL 0x0178 /* 8 bit Blink Source Counter Control */
+#define B2_BSC_STAT 0x0179 /* 8 bit Blink Source Counter Status */
+#define B2_BSC_TST 0x017a /* 16 bit Blink Source Counter Test Reg */
/* 0x017c - 0x017f: reserved */
/*
* Bank 3
*/
-#define B3_RAM_ADDR 0x0180 /* 32 bit RAM Address, to read or write */
+#define B3_RAM_ADDR 0x0180 /* 32 bit RAM Address, to read or write */
#define B3_RAM_DATA_LO 0x0184 /* 32 bit RAM Data Word (low dWord) */
#define B3_RAM_DATA_HI 0x0188 /* 32 bit RAM Data Word (high dWord) */
/* 0x018c - 0x018f: reserved */
@@ -499,7 +501,7 @@
/*
* The HW-Spec. call this registers Timeout Value 0..11. But this names are
* not usable in SW. Please notice these are NOT real timeouts, these are
- * the number of qWords transferred continously.
+ * the number of qWords transfered continously.
*/
#define B3_RI_WTO_R1 0x0190 /* 8 bit RAM Iface WR Timeout Queue R1 (TO0) */
#define B3_RI_WTO_XA1 0x0191 /* 8 bit RAM Iface WR Timeout Queue XA1 (TO1) */
@@ -515,8 +517,8 @@
#define B3_RI_RTO_XS2 0x019b /* 8 bit RAM Iface RD Timeout Queue XS2 (TO11)*/
#define B3_RI_TO_VAL 0x019c /* 8 bit RAM Iface Current Timeout Count Val */
/* 0x019d - 0x019f reserved */
-#define B3_RI_CTRL 0x01a0 /* 16 bit RAM Iface Control Register */
-#define B3_RI_TEST 0x01a2 /* 8 bit RAM Iface Test Register */
+#define B3_RI_CTRL 0x01a0 /* 16 bit RAM Iface Control Register */
+#define B3_RI_TEST 0x01a2 /* 8 bit RAM Iface Test Register */
/* 0x01a3 - 0x01af reserved */
/* MAC Arbiter Registers */
/* Please notice these are the number of qWord tranfered continously and */
@@ -569,42 +571,42 @@
*/
/* Transmit Arbiter Registers MAC 1 and 2, user MR_ADDR() to address */
-#define TXA_ITI_INI 0x0200 /* 32 bit Tx Arb Interval Timer Init Val*/
-#define TXA_ITI_VAL 0x0204 /* 32 bit Tx Arb Interval Timer Value */
-#define TXA_LIM_INI 0x0208 /* 32 bit Tx Arb Limit Counter Init Val */
-#define TXA_LIM_VAL 0x020c /* 32 bit Tx Arb Limit Counter Value */
-#define TXA_CTRL 0x0210 /* 8 bit Tx Arbiter Control Register */
-#define TXA_TEST 0x0211 /* 8 bit Tx Arbiter Test Register */
-#define TXA_STAT 0x0212 /* 8 bit Tx Arbiter Status Register */
+#define TXA_ITI_INI 0x0200 /* 32 bit Tx Arb Interval Timer Init Val*/
+#define TXA_ITI_VAL 0x0204 /* 32 bit Tx Arb Interval Timer Value */
+#define TXA_LIM_INI 0x0208 /* 32 bit Tx Arb Limit Counter Init Val */
+#define TXA_LIM_VAL 0x020c /* 32 bit Tx Arb Limit Counter Value */
+#define TXA_CTRL 0x0210 /* 8 bit Tx Arbiter Control Register */
+#define TXA_TEST 0x0211 /* 8 bit Tx Arbiter Test Register */
+#define TXA_STAT 0x0212 /* 8 bit Tx Arbiter Status Register */
/* 0x0213 - 0x027f: reserved */
/*
* Bank 6
*/
/* External registers */
-#define B6_EXT_REG 0x0300
+#define B6_EXT_REG 0x0300
/*
* Bank 7
*/
/* This is a copy of the Configuration register file (lower half) */
-#define B7_CFG_SPC 0x0380
+#define B7_CFG_SPC 0x0380
/*
* Bank 8 - 15
*/
/* Receive and Transmit Queue Registers, use Q_ADDR() to access */
-#define B8_Q_REGS 0x0400
+#define B8_Q_REGS 0x0400
/* Queue Register Offsets, use Q_ADDR() to access */
-#define Q_D 0x00 /* 8*32 bit Current Descriptor */
+#define Q_D 0x00 /* 8*32 bit Current Descriptor */
#define Q_DA_L 0x20 /* 32 bit Current Descriptor Address Low dWord */
#define Q_DA_H 0x24 /* 32 bit Current Descriptor Address High dWord */
#define Q_AC_L 0x28 /* 32 bit Current Address Counter Low dWord */
#define Q_AC_H 0x2c /* 32 bit Current Address Counter High dWord */
#define Q_BC 0x30 /* 32 bit Current Byte Counter */
#define Q_CSR 0x34 /* 32 bit BMU Control/Status Register */
-#define Q_F 0x38 /* 32 bit Flag Register */
+#define Q_F 0x38 /* 32 bit Flag Register */
#define Q_T1 0x3c /* 32 bit Test Register 1 */
#define Q_T1_TR 0x3c /* 8 bit Test Register 1 Transfer SM */
#define Q_T1_WR 0x3d /* 8 bit Test Register 1 Write Descriptor SM */
@@ -642,64 +644,64 @@
* Bank 24 - 25
*/
/* Receive MAC FIFO, Receive LED, and Link Sync regs, use MR_ADDR() to address*/
-#define RX_MFF_EA 0x0c00 /* 32 bit Receive MAC FIFO End Address */
-#define RX_MFF_WP 0x0c04 /* 32 bit Receive MAC FIFO Write Pointer*/
+#define RX_MFF_EA 0x0c00 /* 32 bit Receive MAC FIFO End Address */
+#define RX_MFF_WP 0x0c04 /* 32 bit Receive MAC FIFO Write Pointer*/
/* 0x0c08 - 0x0c0b reserved */
-#define RX_MFF_RP 0x0c0c /* 32 bit Receive MAC FIFO Read Pointer */
-#define RX_MFF_PC 0x0c10 /* 32 bit Receive MAC FIFO Packet Cnt */
-#define RX_MFF_LEV 0x0c14 /* 32 bit Receive MAC FIFO Level */
+#define RX_MFF_RP 0x0c0c /* 32 bit Receive MAC FIFO Read Pointer */
+#define RX_MFF_PC 0x0c10 /* 32 bit Receive MAC FIFO Packet Cnt */
+#define RX_MFF_LEV 0x0c14 /* 32 bit Receive MAC FIFO Level */
#define RX_MFF_CTRL1 0x0c18 /* 16 bit Receive MAC FIFO Control Reg 1*/
#define RX_MFF_STAT_TO 0x0c1a /* 8 bit Receive MAC Status Timeout */
#define RX_MFF_TIST_TO 0x0c1b /* 8 bit Receive MAC Timestamp Timeout */
#define RX_MFF_CTRL2 0x0c1c /* 8 bit Receive MAC FIFO Control Reg 2*/
-#define RX_MFF_TST1 0x0c1d /* 8 bit Receive MAC FIFO Test Reg 1 */
-#define RX_MFF_TST2 0x0c1e /* 8 bit Receive MAC FIFO Test Reg 2 */
+#define RX_MFF_TST1 0x0c1d /* 8 bit Receive MAC FIFO Test Reg 1 */
+#define RX_MFF_TST2 0x0c1e /* 8 bit Receive MAC FIFO Test Reg 2 */
/* 0x0c1f reserved */
-#define RX_LED_INI 0x0c20 /* 32 bit Receive LED Cnt Init Value */
-#define RX_LED_VAL 0x0c24 /* 32 bit Receive LED Cnt Current Value */
-#define RX_LED_CTRL 0x0c28 /* 8 bit Receive LED Cnt Control Reg */
-#define RX_LED_TST 0x0c29 /* 8 bit Receive LED Cnt Test Register */
+#define RX_LED_INI 0x0c20 /* 32 bit Receive LED Cnt Init Value */
+#define RX_LED_VAL 0x0c24 /* 32 bit Receive LED Cnt Current Value */
+#define RX_LED_CTRL 0x0c28 /* 8 bit Receive LED Cnt Control Reg */
+#define RX_LED_TST 0x0c29 /* 8 bit Receive LED Cnt Test Register */
/* 0x0c2a - 0x0c2f reserved */
#define LNK_SYNC_INI 0x0c30 /* 32 bit Link Sync Cnt Init Value */
#define LNK_SYNC_VAL 0x0c34 /* 32 bit Link Sync Cnt Current Value */
#define LNK_SYNC_CTRL 0x0c38 /* 8 bit Link Sync Cnt Control Register*/
#define LNK_SYNC_TST 0x0c39 /* 8 bit Link Sync Cnt Test Register */
/* 0x0c3a - 0x0c3b reserved */
-#define LNK_LED_REG 0x0c3c /* 8 bit Link LED Register */
+#define LNK_LED_REG 0x0c3c /* 8 bit Link LED Register */
/* 0x0c3d - 0x0c7f reserved */
/*
* Bank 26 - 27
*/
/* Transmit MAC FIFO and Transmit LED Registers, use MR_ADDR() to address */
-#define TX_MFF_EA 0x0d00 /* 32 bit Transmit MAC FIFO End Address */
-#define TX_MFF_WP 0x0d04 /* 32 bit Transmit MAC FIFO WR Pointer */
-#define TX_MFF_WSP 0x0d08 /* 32 bit Transmit MAC FIFO WR Shadow Pt*/
-#define TX_MFF_RP 0x0d0c /* 32 bit Transmit MAC FIFO RD Pointer */
-#define TX_MFF_PC 0x0d10 /* 32 bit Transmit MAC FIFO Packet Cnt */
-#define TX_MFF_LEV 0x0d14 /* 32 bit Transmit MAC FIFO Level */
+#define TX_MFF_EA 0x0d00 /* 32 bit Transmit MAC FIFO End Address */
+#define TX_MFF_WP 0x0d04 /* 32 bit Transmit MAC FIFO WR Pointer */
+#define TX_MFF_WSP 0x0d08 /* 32 bit Transmit MAC FIFO WR Shadow Pt*/
+#define TX_MFF_RP 0x0d0c /* 32 bit Transmit MAC FIFO RD Pointer */
+#define TX_MFF_PC 0x0d10 /* 32 bit Transmit MAC FIFO Packet Cnt */
+#define TX_MFF_LEV 0x0d14 /* 32 bit Transmit MAC FIFO Level */
#define TX_MFF_CTRL1 0x0d18 /* 16 bit Transmit MAC FIFO Ctrl Reg 1 */
-#define TX_MFF_WAF 0x0d1a /* 8 bit Transmit MAC Wait after flush*/
+#define TX_MFF_WAF 0x0d1a /* 8 bit Transmit MAC Wait after flush*/
/* 0x0c1b reserved */
#define TX_MFF_CTRL2 0x0d1c /* 8 bit Transmit MAC FIFO Ctrl Reg 2 */
-#define TX_MFF_TST1 0x0d1d /* 8 bit Transmit MAC FIFO Test Reg 1 */
-#define TX_MFF_TST2 0x0d1e /* 8 bit Transmit MAC FIFO Test Reg 2 */
+#define TX_MFF_TST1 0x0d1d /* 8 bit Transmit MAC FIFO Test Reg 1 */
+#define TX_MFF_TST2 0x0d1e /* 8 bit Transmit MAC FIFO Test Reg 2 */
/* 0x0d1f reserved */
-#define TX_LED_INI 0x0d20 /* 32 bit Transmit LED Cnt Init Value */
-#define TX_LED_VAL 0x0d24 /* 32 bit Transmit LED Cnt Current Val */
-#define TX_LED_CTRL 0x0d28 /* 8 bit Transmit LED Cnt Control Reg */
-#define TX_LED_TST 0x0d29 /* 8 bit Transmit LED Cnt Test Register*/
+#define TX_LED_INI 0x0d20 /* 32 bit Transmit LED Cnt Init Value */
+#define TX_LED_VAL 0x0d24 /* 32 bit Transmit LED Cnt Current Val */
+#define TX_LED_CTRL 0x0d28 /* 8 bit Transmit LED Cnt Control Reg */
+#define TX_LED_TST 0x0d29 /* 8 bit Transmit LED Cnt Test Register*/
/* 0x0d2a - 0x0d7f reserved */
/*
* Bank 28
*/
/* Descriptor Poll Timer Registers */
-#define B28_DPT_INI 0x0e00 /* 32 bit Descriptor Poll Timer Init Val*/
-#define B28_DPT_VAL 0x0e04 /* 32 bit Descriptor Poll Timer Curr Val*/
+#define B28_DPT_INI 0x0e00 /* 32 bit Descriptor Poll Timer Init Val*/
+#define B28_DPT_VAL 0x0e04 /* 32 bit Descriptor Poll Timer Curr Val*/
#define B28_DPT_CTRL 0x0e08 /* 8 bit Descriptor Poll Timer Ctrl Reg*/
/* 0x0e09: reserved */
-#define B28_DPT_TST 0x0e0a /* 8 bit Descriptor Poll Timer Test Reg*/
+#define B28_DPT_TST 0x0e0a /* 8 bit Descriptor Poll Timer Test Reg*/
/* 0x0e0b - 0x0e8f: reserved */
/*
@@ -739,7 +741,7 @@
*/
/* B0_RAP 8 bit Register Address Port */
/* Bit 7: reserved */
-#define RAP_RAP 0x3f /* Bit 6..0: 0 = block 0, .., 6f = block 6f*/
+#define RAP_RAP 0x3f /* Bit 6..0: 0 = block 0, .., 6f = block 6f*/
/* B0_CTST 16 bit Control/Status register */
/* Bit 15..10: reserved */
@@ -749,70 +751,70 @@
#define CS_CL_SW_IRQ (1<<6) /* Bit 6: Clear IRQ SW Request */
#define CS_STOP_DONE (1<<5) /* Bit 5: Stop Master is finished */
#define CS_STOP_MAST (1<<4) /* Bit 4: Command Bit to stop the master*/
-#define CS_MRST_CLR (1<<3) /* Bit 3: Clear Master reset */
-#define CS_MRST_SET (1<<2) /* Bit 2: Set Master reset */
-#define CS_RST_CLR (1<<1) /* Bit 1: Clear Software reset */
-#define CS_RST_SET (1<<0) /* Bit 0: Set Software reset */
+#define CS_MRST_CLR (1<<3) /* Bit 3: Clear Master reset */
+#define CS_MRST_SET (1<<2) /* Bit 2: Set Master reset */
+#define CS_RST_CLR (1<<1) /* Bit 1: Clear Software reset */
+#define CS_RST_SET (1<<0) /* Bit 0: Set Software reset */
/* B0_LED 8 Bit LED register */
/* Bit 7..2: reserved */
-#define LED_STAT_ON (1<<1) /* Bit 1: Status LED on */
+#define LED_STAT_ON (1<<1) /* Bit 1: Status LED on */
#define LED_STAT_OFF (1<<0) /* Bit 0: Status LED off */
/* B0_ISRC 32 bit Interrupt Source Register */
/* B0_IMSK 32 bit Interrupt Mask Register */
/* B0_SP_ISRC 32 bit Special Interrupt Source Reg */
/* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
-#define IS_ALL_MSK 0xbfffffffL /* All Interrupt bits */
-#define IS_HW_ERR (1UL<<31) /* Bit 31: Interrupt HW Error */
- /* Bit 30: reserved */
+#define IS_ALL_MSK 0xbfffffffL /* All Interrupt bits */
+#define IS_HW_ERR (1UL<<31) /* Bit 31: Interrupt HW Error */
+ /* Bit 30: reserved */
#define IS_PA_TO_RX1 (1L<<29) /* Bit 29: Packet Arb Timeout Rx1*/
#define IS_PA_TO_RX2 (1L<<28) /* Bit 28: Packet Arb Timeout Rx2*/
#define IS_PA_TO_TX1 (1L<<27) /* Bit 27: Packet Arb Timeout Tx1*/
#define IS_PA_TO_TX2 (1L<<26) /* Bit 26: Packet Arb Timeout Tx2*/
#define IS_I2C_READY (1L<<25) /* Bit 25: IRQ on end of I2C tx */
-#define IS_IRQ_SW (1L<<24) /* Bit 24: SW forced IRQ */
-#define IS_EXT_REG (1L<<23) /* Bit 23: IRQ from external reg */
-#define IS_TIMINT (1L<<22) /* Bit 22: IRQ from Timer */
-#define IS_MAC1 (1L<<21) /* Bit 21: IRQ from MAC 1 */
+#define IS_IRQ_SW (1L<<24) /* Bit 24: SW forced IRQ */
+#define IS_EXT_REG (1L<<23) /* Bit 23: IRQ from external reg */
+#define IS_TIMINT (1L<<22) /* Bit 22: IRQ from Timer */
+#define IS_MAC1 (1L<<21) /* Bit 21: IRQ from MAC 1 */
#define IS_LNK_SYNC_M1 (1L<<20) /* Bit 20: Link Sync Cnt wrap M1 */
-#define IS_MAC2 (1L<<19) /* Bit 19: IRQ from MAC 2 */
+#define IS_MAC2 (1L<<19) /* Bit 19: IRQ from MAC 2 */
#define IS_LNK_SYNC_M2 (1L<<18) /* Bit 18: Link Sync Cnt wrap M2 */
/* Receive Queue 1 */
-#define IS_R1_B (1L<<17) /* Bit 17: Q_R1 End of Buffer */
-#define IS_R1_F (1L<<16) /* Bit 16: Q_R1 End of Frame */
-#define IS_R1_C (1L<<15) /* Bit 15: Q_R1 Encoding Error */
+#define IS_R1_B (1L<<17) /* Bit 17: Q_R1 End of Buffer */
+#define IS_R1_F (1L<<16) /* Bit 16: Q_R1 End of Frame */
+#define IS_R1_C (1L<<15) /* Bit 15: Q_R1 Encoding Error */
/* Receive Queue 2 */
-#define IS_R2_B (1L<<14) /* Bit 14: Q_R2 End of Buffer */
-#define IS_R2_F (1L<<13) /* Bit 13: Q_R2 End of Frame */
-#define IS_R2_C (1L<<12) /* Bit 12: Q_R2 Encoding Error */
+#define IS_R2_B (1L<<14) /* Bit 14: Q_R2 End of Buffer */
+#define IS_R2_F (1L<<13) /* Bit 13: Q_R2 End of Frame */
+#define IS_R2_C (1L<<12) /* Bit 12: Q_R2 Encoding Error */
/* Synchronous Transmit Queue 1 */
-#define IS_XS1_B (1L<<11) /* Bit 11: Q_XS1 End of Buffer */
-#define IS_XS1_F (1L<<10) /* Bit 10: Q_XS1 End of Frame */
-#define IS_XS1_C (1L<<9) /* Bit 9: Q_XS1 Encoding Error */
+#define IS_XS1_B (1L<<11) /* Bit 11: Q_XS1 End of Buffer */
+#define IS_XS1_F (1L<<10) /* Bit 10: Q_XS1 End of Frame */
+#define IS_XS1_C (1L<<9) /* Bit 9: Q_XS1 Encoding Error */
/* Asynchronous Transmit Queue 1 */
-#define IS_XA1_B (1L<<8) /* Bit 8: Q_XA1 End of Buffer */
-#define IS_XA1_F (1L<<7) /* Bit 7: Q_XA1 End of Frame */
-#define IS_XA1_C (1L<<6) /* Bit 6: Q_XA1 Encoding Error */
+#define IS_XA1_B (1L<<8) /* Bit 8: Q_XA1 End of Buffer */
+#define IS_XA1_F (1L<<7) /* Bit 7: Q_XA1 End of Frame */
+#define IS_XA1_C (1L<<6) /* Bit 6: Q_XA1 Encoding Error */
/* Synchronous Transmit Queue 2 */
-#define IS_XS2_B (1L<<5) /* Bit 5: Q_XS2 End of Buffer */
-#define IS_XS2_F (1L<<4) /* Bit 4: Q_XS2 End of Frame */
-#define IS_XS2_C (1L<<3) /* Bit 3: Q_XS2 Encoding Error */
+#define IS_XS2_B (1L<<5) /* Bit 5: Q_XS2 End of Buffer */
+#define IS_XS2_F (1L<<4) /* Bit 4: Q_XS2 End of Frame */
+#define IS_XS2_C (1L<<3) /* Bit 3: Q_XS2 Encoding Error */
/* Asynchronous Transmit Queue 2 */
-#define IS_XA2_B (1L<<2) /* Bit 2: Q_XA2 End of Buffer */
-#define IS_XA2_F (1L<<1) /* Bit 1: Q_XA2 End of Frame */
-#define IS_XA2_C (1L<<0) /* Bit 0: Q_XA2 Encoding Error */
+#define IS_XA2_B (1L<<2) /* Bit 2: Q_XA2 End of Buffer */
+#define IS_XA2_F (1L<<1) /* Bit 1: Q_XA2 End of Frame */
+#define IS_XA2_C (1L<<0) /* Bit 0: Q_XA2 Encoding Error */
/* B0_HWE_ISRC 32 bit HW Error Interrupt Src Reg */
/* B0_HWE_IMSK 32 bit HW Error Interrupt Mask Reg */
/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
-#define IS_ERR_MSK 0x00000fffL /* All Error bits */
- /* Bit 31..12: reserved */
+#define IS_ERR_MSK 0x00000fffL /* All Error bits */
+ /* Bit 31..12: reserved */
#define IS_IRQ_MST_ERR (1L<<11) /* Bit 11: IRQ master error */
- /* PERR,RMABORT,RTABORT,DATAPERR */
-#define IS_IRQ_STAT (1L<<10) /* Bit 10: IRQ status execption */
- /* RMABORT, RTABORT, DATAPERR */
+ /* PERR,RMABORT,RTABORT,DATAPERR */
+#define IS_IRQ_STAT (1L<<10) /* Bit 10: IRQ status execption */
+ /* RMABORT, RTABORT, DATAPERR */
#define IS_NO_STAT_M1 (1L<<9) /* Bit 9: No Rx Status from MAC1*/
#define IS_NO_STAT_M2 (1L<<8) /* Bit 8: No Rx Status from MAC2*/
#define IS_NO_TIST_M1 (1L<<7) /* Bit 7: No Timestamp from MAC1*/
@@ -829,53 +831,53 @@
/* Values of connector and PMD type comply to SysKonnect internal std */
/* B2_MAC_CFG 8 bit MAC Configuration */
- /* Bit 7..2: reserved */
+ /* Bit 7..2: reserved */
#define CFG_DIS_M2_CLK (1<<1) /* Bit 1: Disable Clock for 2nd MAC */
-#define CFG_SNG_MAC (1<<0) /* Bit 0: MAC Config: 1=2 MACs / 0=1 MAC*/
+#define CFG_SNG_MAC (1<<0) /* Bit 0: MAC Config: 1=2 MACs / 0=1 MAC*/
/* B2_CHIP_REV 8 bit Queen Chip Revision Number */
#define FIRST_CHIP_REV 0x0a /* Initial Revision Value */
/* B2_FAR 32 bit Flash-Prom Addr Reg/Cnt */
-#define FAR_ADDR 0x1ffffL /* Bit 16..0: FPROM Address mask */
+#define FAR_ADDR 0x1ffffL /* Bit 16..0: FPROM Address mask */
/* B2_LD_CRTL 8 bit EPROM loader control register */
/* Bits are currently reserved */
/* B2_LD_TEST 8 bit EPROM loader test register */
- /* Bit 7..4: reserved */
-#define LD_T_ON (1<<3) /* Bit 3: Loader Testmode on */
-#define LD_T_OFF (1<<2) /* Bit 2: Loader Testmode off */
-#define LD_T_STEP (1<<1) /* Bit 1: Decrement FPROM addr. Counter */
-#define LD_START (1<<0) /* Bit 0: Start loading FPROM */
+ /* Bit 7..4: reserved */
+#define LD_T_ON (1<<3) /* Bit 3: Loader Testmode on */
+#define LD_T_OFF (1<<2) /* Bit 2: Loader Testmode off */
+#define LD_T_STEP (1<<1) /* Bit 1: Decrement FPROM addr. Counter */
+#define LD_START (1<<0) /* Bit 0: Start loading FPROM */
/*
* Timer Section
*/
/* B2_TI_CRTL 8 bit Timer control */
/* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
- /* Bit 7..3: reserved */
-#define TIM_START (1<<2) /* Bit 2: Start Timer */
-#define TIM_STOP (1<<1) /* Bit 1: Stop Timer */
-#define TIM_CLR_IRQ (1<<0) /* Bit 0: Clear Timer IRQ, (!IRQM) */
+ /* Bit 7..3: reserved */
+#define TIM_START (1<<2) /* Bit 2: Start Timer */
+#define TIM_STOP (1<<1) /* Bit 1: Stop Timer */
+#define TIM_CLR_IRQ (1<<0) /* Bit 0: Clear Timer IRQ, (!IRQM) */
/* B2_TI_TEST 8 Bit Timer Test */
/* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
/* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
- /* Bit 7..3: reserved */
-#define TIM_T_ON (1<<2) /* Bit 2: Test mode on */
-#define TIM_T_OFF (1<<1) /* Bit 1: Test mode off */
-#define TIM_T_STEP (1<<0) /* Bit 0: Test step */
+ /* Bit 7..3: reserved */
+#define TIM_T_ON (1<<2) /* Bit 2: Test mode on */
+#define TIM_T_OFF (1<<1) /* Bit 1: Test mode off */
+#define TIM_T_STEP (1<<0) /* Bit 0: Test step */
/* B28_DPT_INI 32 bit Descriptor Poll Timer Init Val */
/* B28_DPT_VAL 32 bit Descriptor Poll Timer Curr Val */
- /* Bit 31..24: reserved */
-#define DPT_MSK 0x00ffffffL /* Bit 23.. 0: Desc Poll Timer Bits */
+ /* Bit 31..24: reserved */
+#define DPT_MSK 0x00ffffffL /* Bit 23.. 0: Desc Poll Timer Bits */
/* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */
- /* Bit 7..2: reserved */
-#define DPT_START (1<<1) /* Bit 1: Start Desciptor Poll Timer */
-#define DPT_STOP (1<<0) /* Bit 0: Stop Desciptor Poll Timer */
+ /* Bit 7..2: reserved */
+#define DPT_START (1<<1) /* Bit 1: Start Desciptor Poll Timer */
+#define DPT_STOP (1<<0) /* Bit 0: Stop Desciptor Poll Timer */
/* B2_TST_CTRL1 8 bit Test Control Register 1 */
@@ -889,7 +891,7 @@
#define TST_CFG_WRITE_OFF (1<<0) /* Bit 0: Disable Config Reg WR */
/* B2_TST_CTRL2 8 bit Test Control Register 2 */
- /* Bit 7..4: reserved */
+ /* Bit 7..4: reserved */
/* force the following error on */
/* the next master read/write */
#define TST_FRC_DPERR_MR64 (1<<3) /* Bit 3: DataPERR RD 64 */
@@ -898,7 +900,7 @@
#define TST_FRC_APERR_2M64 (1<<0) /* Bit 0: AddrPERR on 2. phase */
/* B2_GP_IO 32 bit General Purpose IO Register */
- /* Bit 31..26: reserved */
+ /* Bit 31..26: reserved */
#define GP_DIR_9 (1L<<25) /* Bit 25: IO_9 direct, 0=I/1=O */
#define GP_DIR_8 (1L<<24) /* Bit 24: IO_8 direct, 0=I/1=O */
#define GP_DIR_7 (1L<<23) /* Bit 23: IO_7 direct, 0=I/1=O */
@@ -909,7 +911,7 @@
#define GP_DIR_2 (1L<<18) /* Bit 18: IO_2 direct, 0=I/1=O */
#define GP_DIR_1 (1L<<17) /* Bit 17: IO_1 direct, 0=I/1=O */
#define GP_DIR_0 (1L<<16) /* Bit 16: IO_0 direct, 0=I/1=O */
- /* Bit 15..10: reserved */
+ /* Bit 15..10: reserved */
#define GP_IO_9 (1L<<9) /* Bit 9: IO_9 pin */
#define GP_IO_8 (1L<<8) /* Bit 8: IO_8 pin */
#define GP_IO_7 (1L<<7) /* Bit 7: IO_7 pin */
@@ -922,31 +924,31 @@
#define GP_IO_0 (1L<<0) /* Bit 0: IO_0 pin */
/* B2_I2C_CTRL 32 bit I2C HW Control Register */
-#define I2C_FLAG (1UL<<31) /* Bit 31: Start read/write if WR*/
+#define I2C_FLAG (1UL<<31) /* Bit 31: Start read/write if WR*/
#define I2C_ADDR (0x7fffL<<16) /* Bit 30..16: Addr to be RD/WR */
-#define I2C_DEV_SEL (0x7fL<<9) /* Bit 15.. 9: I2C Device Select */
- /* Bit 8.. 5: reserved */
+#define I2C_DEV_SEL (0x7fL<<9) /* Bit 15.. 9: I2C Device Select */
+ /* Bit 8.. 5: reserved */
#define I2C_BURST_LEN (1L<<4) /* Bit 4: Burst Len, 1/4 bytes */
#define I2C_DEV_SIZE (7L<<1) /* Bit 3.. 1: I2C Device Size */
#define I2C_025K_DEV (0L<<1) /* 0: 256 Bytes or smal. */
-#define I2C_05K_DEV (1L<<1) /* 1: 512 Bytes */
-#define I2C_1K_DEV (2L<<1) /* 2: 1024 Bytes */
-#define I2C_2K_DEV (3L<<1) /* 3: 2048 Bytes */
-#define I2C_4K_DEV (4L<<1) /* 4: 4096 Bytes */
-#define I2C_8K_DEV (5L<<1) /* 5: 8192 Bytes */
-#define I2C_16K_DEV (6L<<1) /* 6: 16384 Bytes */
-#define I2C_32K_DEV (7L<<1) /* 7: 32768 Bytes */
-#define I2C_STOP (1L<<0) /* Bit 0: Interrupt I2C transfer*/
+#define I2C_05K_DEV (1L<<1) /* 1: 512 Bytes */
+#define I2C_1K_DEV (2L<<1) /* 2: 1024 Bytes */
+#define I2C_2K_DEV (3L<<1) /* 3: 2048 Bytes */
+#define I2C_4K_DEV (4L<<1) /* 4: 4096 Bytes */
+#define I2C_8K_DEV (5L<<1) /* 5: 8192 Bytes */
+#define I2C_16K_DEV (6L<<1) /* 6: 16384 Bytes */
+#define I2C_32K_DEV (7L<<1) /* 7: 32768 Bytes */
+#define I2C_STOP (1L<<0) /* Bit 0: Interrupt I2C transfer*/
/* B2_I2C_IRQ 32 bit I2C HW IRQ Register */
- /* Bit 31..1 reserved */
-#define I2C_CLR_IRQ (1<<0) /* Bit 0: Clear I2C IRQ */
+ /* Bit 31..1 reserved */
+#define I2C_CLR_IRQ (1<<0) /* Bit 0: Clear I2C IRQ */
/* B2_I2C_SW 32 bit I2C HW SW Port Register */
- /* Bit 7..3: reserved */
+ /* Bit 7..3: reserved */
#define I2C_DATA_DIR (1<<2) /* Bit 2: direction of I2C_DATA */
-#define I2C_DATA (1<<1) /* Bit 1: I2C Data Port */
-#define I2C_CLK (1<<0) /* Bit 0: I2C Clock Port */
+#define I2C_DATA (1<<1) /* Bit 1: I2C Data Port */
+#define I2C_CLK (1<<0) /* Bit 0: I2C Clock Port */
/*
* I2C Address
@@ -955,12 +957,12 @@
/* B2_BSC_CTRL 8 bit Blink Source Counter Control */
- /* Bit 7..2: reserved */
+ /* Bit 7..2: reserved */
#define BSC_START (1<<1) /* Bit 1: Start Blink Source Counter */
#define BSC_STOP (1<<0) /* Bit 0: Stop Blink Source Counter */
/* B2_BSC_STAT 8 bit Blink Source Counter Status */
- /* Bit 7..1: reserved */
+ /* Bit 7..1: reserved */
#define BSC_SRC (1<<0) /* Bit 0: Blink Source, 0=Off / 1=On */
/* B2_BSC_TST 16 bit Blink Source Counter Test Reg */
@@ -975,30 +977,30 @@
/* RAM Interface Registers */
/* B3_RI_CTRL 16 bit RAM Iface Control Register */
- /* Bit 15..10: reserved */
+ /* Bit 15..10: reserved */
#define RI_CLR_RD_PERR (1<<9) /* Bit 9: Clear IRQ RAM Read Parity Err */
#define RI_CLR_WR_PERR (1<<8) /* Bit 8: Clear IRQ RAM Write Parity Err*/
- /* Bit 7..2: reserved */
-#define RI_RST_CLR (1<<1) /* Bit 1: Clear RAM Interface Reset */
-#define RI_RST_SET (1<<0) /* Bit 0: Set RAM Interface Reset */
+ /* Bit 7..2: reserved */
+#define RI_RST_CLR (1<<1) /* Bit 1: Clear RAM Interface Reset */
+#define RI_RST_SET (1<<0) /* Bit 0: Set RAM Interface Reset */
/* B3_RI_TEST 8 bit RAM Iface Test Register */
- /* Bit 15..4: reserved */
-#define RI_T_EV (1<<3) /* Bit 3: Timeout Event occurred */
-#define RI_T_ON (1<<2) /* Bit 2: Timeout Timer Test On */
-#define RI_T_OFF (1<<1) /* Bit 1: Timeout Timer Test Off */
-#define RI_T_STEP (1<<0) /* Bit 0: Timeout Timer Step */
+ /* Bit 15..4: reserved */
+#define RI_T_EV (1<<3) /* Bit 3: Timeout Event occured */
+#define RI_T_ON (1<<2) /* Bit 2: Timeout Timer Test On */
+#define RI_T_OFF (1<<1) /* Bit 1: Timeout Timer Test Off */
+#define RI_T_STEP (1<<0) /* Bit 0: Timeout Timer Step */
/* MAC Arbiter Registers */
/* B3_MA_TO_CTRL 16 bit MAC Arbiter Timeout Ctrl Reg */
- /* Bit 15..4: reserved */
-#define MA_FOE_ON (1<<3) /* Bit 3: XMAC Fast Output Enable ON */
-#define MA_FOE_OFF (1<<2) /* Bit 2: XMAC Fast Output Enable OFF */
-#define MA_RST_CLR (1<<1) /* Bit 1: Clear MAC Arbiter Reset */
-#define MA_RST_SET (1<<0) /* Bit 0: Set MAC Arbiter Reset */
+ /* Bit 15..4: reserved */
+#define MA_FOE_ON (1<<3) /* Bit 3: XMAC Fast Output Enable ON */
+#define MA_FOE_OFF (1<<2) /* Bit 2: XMAC Fast Output Enable OFF */
+#define MA_RST_CLR (1<<1) /* Bit 1: Clear MAC Arbiter Reset */
+#define MA_RST_SET (1<<0) /* Bit 0: Set MAC Arbiter Reset */
/* B3_MA_RC_CTRL 16 bit MAC Arbiter Recovery Ctrl Reg */
- /* Bit 15..8: reserved */
+ /* Bit 15..8: reserved */
#define MA_ENA_REC_TX2 (1<<7) /* Bit 7: Enable Recovery Timer TX2 */
#define MA_DIS_REC_TX2 (1<<6) /* Bit 6: Disable Recovery Timer TX2 */
#define MA_ENA_REC_TX1 (1<<5) /* Bit 5: Enable Recovery Timer TX1 */
@@ -1010,7 +1012,7 @@
/* Packet Arbiter Registers */
/* B3_PA_CTRL 16 bit Packet Arbiter Ctrl Register */
- /* Bit 15..14: reserved */
+ /* Bit 15..14: reserved */
#define PA_CLR_TO_TX2 (1<<13) /* Bit 13: Clear IRQ Packet Timeout TX2 */
#define PA_CLR_TO_TX1 (1<<12) /* Bit 12: Clear IRQ Packet Timeout TX1 */
#define PA_CLR_TO_RX2 (1<<11) /* Bit 11: Clear IRQ Packet Timeout RX2 */
@@ -1023,30 +1025,30 @@
#define PA_DIS_TO_RX2 (1<<4) /* Bit 4: Disable Timeout Timer RX2 */
#define PA_ENA_TO_RX1 (1<<3) /* Bit 3: Enable Timeout Timer RX1 */
#define PA_DIS_TO_RX1 (1<<2) /* Bit 2: Disable Timeout Timer RX1 */
-#define PA_RST_CLR (1<<1) /* Bit 1: Clear MAC Arbiter Reset */
-#define PA_RST_SET (1<<0) /* Bit 0: Set MAC Arbiter Reset */
+#define PA_RST_CLR (1<<1) /* Bit 1: Clear MAC Arbiter Reset */
+#define PA_RST_SET (1<<0) /* Bit 0: Set MAC Arbiter Reset */
#define PA_ENA_TO_ALL (PA_ENA_TO_RX1 | PA_ENA_TO_RX2 |\
- PA_ENA_TO_TX1 | PA_ENA_TO_TX2)
+ PA_ENA_TO_TX1 | PA_ENA_TO_TX2)
/* Rx/Tx Path related Arbiter Test Registers */
/* B3_MA_TO_TEST 16 bit MAC Arbiter Timeout Test Reg */
/* B3_MA_RC_TEST 16 bit MAC Arbiter Recovery Test Reg */
/* B3_PA_TEST 16 bit Packet Arbiter Test Register */
/* Bit 15, 11, 7, and 3 are reserved in B3_PA_TEST */
-#define TX2_T_EV (1<<15) /* Bit 15: TX2 Timeout/Recv Event occurred*/
+#define TX2_T_EV (1<<15) /* Bit 15: TX2 Timeout/Recv Event occured*/
#define TX2_T_ON (1<<14) /* Bit 14: TX2 Timeout/Recv Timer Test On*/
#define TX2_T_OFF (1<<13) /* Bit 13: TX2 Timeout/Recv Timer Tst Off*/
#define TX2_T_STEP (1<<12) /* Bit 12: TX2 Timeout/Recv Timer Step */
-#define TX1_T_EV (1<<11) /* Bit 11: TX1 Timeout/Recv Event occurred*/
+#define TX1_T_EV (1<<11) /* Bit 11: TX1 Timeout/Recv Event occured*/
#define TX1_T_ON (1<<10) /* Bit 10: TX1 Timeout/Recv Timer Test On*/
#define TX1_T_OFF (1<<9) /* Bit 9: TX1 Timeout/Recv Timer Tst Off*/
#define TX1_T_STEP (1<<8) /* Bit 8: TX1 Timeout/Recv Timer Step */
-#define RX2_T_EV (1<<7) /* Bit 7: RX2 Timeout/Recv Event occurred*/
+#define RX2_T_EV (1<<7) /* Bit 7: RX2 Timeout/Recv Event occured*/
#define RX2_T_ON (1<<6) /* Bit 6: RX2 Timeout/Recv Timer Test On*/
#define RX2_T_OFF (1<<5) /* Bit 5: RX2 Timeout/Recv Timer Tst Off*/
#define RX2_T_STEP (1<<4) /* Bit 4: RX2 Timeout/Recv Timer Step */
-#define RX1_T_EV (1<<3) /* Bit 3: RX1 Timeout/Recv Event occurred*/
+#define RX1_T_EV (1<<3) /* Bit 3: RX1 Timeout/Recv Event occured*/
#define RX1_T_ON (1<<2) /* Bit 2: RX1 Timeout/Recv Timer Test On*/
#define RX1_T_OFF (1<<1) /* Bit 1: RX1 Timeout/Recv Timer Tst Off*/
#define RX1_T_STEP (1<<0) /* Bit 0: RX1 Timeout/Recv Timer Step */
@@ -1057,7 +1059,7 @@
/* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
/* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
/* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
- /* Bit 31..24: reserved */
+ /* Bit 31..24: reserved */
#define TXA_MAX_VAL 0x00ffffffL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
/* TXA_CTRL 8 bit Tx Arbiter Control Register */
@@ -1066,9 +1068,9 @@
#define TXA_ENA_ALLOC (1<<5) /* Bit 5: Enable alloc of free bandwidth*/
#define TXA_DIS_ALLOC (1<<4) /* Bit 4: Disabl alloc of free bandwidth*/
#define TXA_START_RC (1<<3) /* Bit 3: Start sync Rate Control */
-#define TXA_STOP_RC (1<<2) /* Bit 2: Stop sync Rate Control */
-#define TXA_ENA_ARB (1<<1) /* Bit 1: Enable Tx Arbiter */
-#define TXA_DIS_ARB (1<<0) /* Bit 0: Disable Tx Arbiter */
+#define TXA_STOP_RC (1<<2) /* Bit 2: Stop sync Rate Control */
+#define TXA_ENA_ARB (1<<1) /* Bit 1: Enable Tx Arbiter */
+#define TXA_DIS_ARB (1<<0) /* Bit 0: Disable Tx Arbiter */
/* TXA_TEST 8 bit Tx Arbiter Test Register */
/* Bit 7..6: reserved */
@@ -1080,12 +1082,12 @@
#define TXA_LIM_T_STEP (1<<0) /* Bit 0: Tx Arb Limit Timer Step */
/* TXA_STAT 8 bit Tx Arbiter Status Register */
- /* Bit 7..1: reserved */
-#define TXA_PRIO_XS (1<<0) /* Bit 0: sync queue has prio to send */
+ /* Bit 7..1: reserved */
+#define TXA_PRIO_XS (1<<0) /* Bit 0: sync queue has prio to send */
/* Q_BC 32 bit Current Byte Counter */
/* Bit 31..16: reserved */
-#define BC_MAX 0xffff /* Bit 15.. 0: Byte counter */
+#define BC_MAX 0xffff /* Bit 15.. 0: Byte counter */
/* BMU Control Status Registers */
/* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
@@ -1095,47 +1097,47 @@
/* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
/* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
/* Q_CSR 32 bit BMU Control/Status Register */
- /* Bit 31..25: reserved */
-#define CSR_SV_IDLE (1L<<24) /* Bit 24: BMU SM Idle */
- /* Bit 23..22: reserved */
+ /* Bit 31..25: reserved */
+#define CSR_SV_IDLE (1L<<24) /* Bit 24: BMU SM Idle */
+ /* Bit 23..22: reserved */
#define CSR_DESC_CLR (1L<<21) /* Bit 21: Clear Reset for Descr */
#define CSR_DESC_SET (1L<<20) /* Bit 20: Set Reset for Descr */
#define CSR_FIFO_CLR (1L<<19) /* Bit 19: Clear Reset for FIFO */
#define CSR_FIFO_SET (1L<<18) /* Bit 18: Set Reset for FIFO */
-#define CSR_HPI_RUN (1L<<17) /* Bit 17: Release HPI SM */
-#define CSR_HPI_RST (1L<<16) /* Bit 16: Reset HPI SM to Idle */
-#define CSR_SV_RUN (1L<<15) /* Bit 15: Release Supervisor SM */
-#define CSR_SV_RST (1L<<14) /* Bit 14: Reset Supervisor SM */
+#define CSR_HPI_RUN (1L<<17) /* Bit 17: Release HPI SM */
+#define CSR_HPI_RST (1L<<16) /* Bit 16: Reset HPI SM to Idle */
+#define CSR_SV_RUN (1L<<15) /* Bit 15: Release Supervisor SM */
+#define CSR_SV_RST (1L<<14) /* Bit 14: Reset Supervisor SM */
#define CSR_DREAD_RUN (1L<<13) /* Bit 13: Release Descr Read SM */
#define CSR_DREAD_RST (1L<<12) /* Bit 12: Reset Descr Read SM */
#define CSR_DWRITE_RUN (1L<<11) /* Bit 11: Rel. Descr Write SM */
#define CSR_DWRITE_RST (1L<<10) /* Bit 10: Reset Descr Write SM */
#define CSR_TRANS_RUN (1L<<9) /* Bit 9: Release Transfer SM */
#define CSR_TRANS_RST (1L<<8) /* Bit 8: Reset Transfer SM */
-#define CSR_ENA_POL (1L<<7) /* Bit 7: Enable Descr Polling */
-#define CSR_DIS_POL (1L<<6) /* Bit 6: Disable Descr Polling */
-#define CSR_STOP (1L<<5) /* Bit 5: Stop Rx/Tx Queue */
-#define CSR_START (1L<<4) /* Bit 4: Start Rx/Tx Queue */
+#define CSR_ENA_POL (1L<<7) /* Bit 7: Enable Descr Polling */
+#define CSR_DIS_POL (1L<<6) /* Bit 6: Disable Descr Polling */
+#define CSR_STOP (1L<<5) /* Bit 5: Stop Rx/Tx Queue */
+#define CSR_START (1L<<4) /* Bit 4: Start Rx/Tx Queue */
#define CSR_IRQ_CL_P (1L<<3) /* Bit 3: (Rx) Clear Parity IRQ */
#define CSR_IRQ_CL_B (1L<<2) /* Bit 2: Clear EOB IRQ */
#define CSR_IRQ_CL_F (1L<<1) /* Bit 1: Clear EOF IRQ */
#define CSR_IRQ_CL_C (1L<<0) /* Bit 0: Clear ERR IRQ */
#define CSR_SET_RESET (CSR_DESC_SET|CSR_FIFO_SET|CSR_HPI_RST|CSR_SV_RST|\
- CSR_DREAD_RST|CSR_DWRITE_RST|CSR_TRANS_RST)
+ CSR_DREAD_RST|CSR_DWRITE_RST|CSR_TRANS_RST)
#define CSR_CLR_RESET (CSR_DESC_CLR|CSR_FIFO_CLR|CSR_HPI_RUN|CSR_SV_RUN|\
- CSR_DREAD_RUN|CSR_DWRITE_RUN|CSR_TRANS_RUN)
+ CSR_DREAD_RUN|CSR_DWRITE_RUN|CSR_TRANS_RUN)
/* Q_F 32 bit Flag Register */
/* Bit 28..31: reserved */
-#define F_ALM_FULL (1L<<27) (Rx) /* Bit 27: (Rx) FIFO almost full */
-#define F_EMPTY (1L<<27) (Tx) /* Bit 27: (Tx) FIFO empty flag */
-#define F_FIFO_EOF (1L<<26) /* Bit 26: Fag bit in FIFO */
+#define F_ALM_FULL (1L<<27) (Rx) /* Bit 27: (Rx) FIFO almost full */
+#define F_EMPTY (1L<<27) (Tx) /* Bit 27: (Tx) FIFO empty flag */
+#define F_FIFO_EOF (1L<<26) /* Bit 26: Fag bit in FIFO */
#define F_WM_REACHED (1L<<25) /* Bit 25: Watermark reached */
- /* Bit 24: reserved */
+ /* Bit 24: reserved */
#define F_FIFO_LEVEL (0x1fL<<16) /* Bit 23..16: # of Qwords in FIFO */
- /* Bit 15..11: reserved */
+ /* Bit 15..11: reserved */
#define F_WATER_MARK 0x0007ffL /* Bit 10.. 0: Watermark */
/* Q_T1 32 bit Test Register 1 */
@@ -1169,9 +1171,9 @@
#define T2_STEP01 (1<<0) /* Bit 0: Inc AC/Dec BC by 1 */
/* Q_T3 32 bit Test Register 3 */
- /* Bit 31..7: reserved */
+ /* Bit 31..7: reserved */
#define T3_MUX (7<<4) /* Bit 6.. 4: Mux Position */
- /* Bit 3: reserved */
+ /* Bit 3: reserved */
#define T3_VRAM (7<<0) /* Bit 2.. 0: Virtual RAM Buffer Address */
/* RAM Buffer Register Offsets */
@@ -1190,7 +1192,7 @@
#define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
/* RB_TST2 8 bit RAM Buffer Test Register 2 */
- /* Bit 4..7: reserved */
+ /* Bit 4..7: reserved */
#define RB_PC_DEC (1<<3) /* Bit 3: Packet Counter Decrem */
#define RB_PC_T_ON (1<<2) /* Bit 2: Packet Counter Test On */
#define RB_PC_T_OFF (1<<1) /* Bit 1: Packet Counter Tst Off */
@@ -1201,19 +1203,19 @@
#define RB_WP_T_ON (1<<6) /* Bit 6: Write Pointer Test On */
#define RB_WP_T_OFF (1<<5) /* Bit 5: Write Pointer Test Off */
#define RB_WP_INC (1<<4) /* Bit 4: Write Pointer Increm */
- /* Bit 3: reserved */
+ /* Bit 3: reserved */
#define RB_RP_T_ON (1<<2) /* Bit 2: Read Pointer Test On */
#define RB_RP_T_OFF (1<<1) /* Bit 1: Read Pointer Test Off */
#define RB_RP_DEC (1<<0) /* Bit 0: Read Pointer Decrement */
/* RB_CTRL 8 bit RAM Buffer Control Register */
- /* Bit 7..6: reserved */
+ /* Bit 7..6: reserved */
#define RB_ENA_STFWD (1<<5) /* Bit 5: Enable Store & Forward */
#define RB_DIS_STFWD (1<<4) /* Bit 4: Disab. Store & Forward */
#define RB_ENA_OP_MD (1<<3) /* Bit 3: Enable Operation Mode */
#define RB_DIS_OP_MD (1<<2) /* Bit 2: Disab. Operation Mode */
-#define RB_RST_CLR (1<<1) /* Bit 1: Clr RAM Buf STM Reset */
-#define RB_RST_SET (1<<0) /* Bit 0: Set RAM Buf STM Reset */
+#define RB_RST_CLR (1<<1) /* Bit 1: Clr RAM Buf STM Reset */
+#define RB_RST_SET (1<<0) /* Bit 0: Set RAM Buf STM Reset */
/* Receive and Transmit MAC FIFO Registers, use MR_ADDR() to address */
@@ -1228,11 +1230,11 @@
/* TX_MFF_RP 32 bit Transmit MAC FIFO Read Pointer */
/* TX_MFF_PC 32 bit Transmit MAC FIFO Packet Cnt */
/* TX_MFF_LEV 32 bit Transmit MAC FIFO Level */
- /* Bit 31..6: reserved */
+ /* Bit 31..6: reserved */
#define MFF_MSK 0x007fL /* Bit 5..0: MAC FIFO Address/Pointer Bits */
/* RX_MFF_CTRL1 16 bit Receive MAC FIFO Control Reg 1 */
- /* Bit 15..14: reserved */
+ /* Bit 15..14: reserved */
#define MFF_ENA_RDY_PAT (1<<13) /* Bit 13: Enable Ready Patch */
#define MFF_DIS_RDY_PAT (1<<12) /* Bit 12: Disable Ready Patch */
#define MFF_ENA_TIM_PAT (1<<11) /* Bit 11: Enable Timing Patch */
@@ -1252,15 +1254,15 @@
/* TX_MFF_CTRL1 16 bit Transmit MAC FIFO Control Reg 1 */
#define MFF_CLR_PERR (1<<15) /* Bit 15: Clear Parity Error IRQ*/
- /* Bit 14: reserved */
+ /* Bit 14: reserved */
#define MFF_ENA_PKT_REC (1<<13) /* Bit 13: Enable Packet Recovery*/
#define MFF_DIS_PKT_REC (1<<12) /* Bit 12: Disable Packet Recov. */
/* MFF_ENA_TIM_PAT (see RX_MFF_CTRL1)Bit 11: Enable Timing Patch */
/* MFF_DIS_TIM_PAT (see RX_MFF_CTRL1)Bit 10: Disable Timing Patch */
/* MFF_ENA_ALM_FUL (see RX_MFF_CTRL1)Bit 9: Enable AlmostFull Sign*/
/* MFF_DIS_ALM_FUL (see RX_MFF_CTRL1)Bit 8: Disab. AlmostFull Sign*/
-#define MFF_ENA_W4E (1<<7) /* Bit 7: Enable Wait for Empty */
-#define MFF_DIS_W4E (1<<6) /* Bit 6: Disab. Wait for Empty */
+#define MFF_ENA_W4E (1<<7) /* Bit 7: Enable Wait for Empty */
+#define MFF_DIS_W4E (1<<6) /* Bit 6: Disab. Wait for Empty */
/* MFF_ENA_FLUSH (see RX_MFF_CTRL1)Bit 5: Enable Frame Flushing */
/* MFF_DIS_FLUSH (see RX_MFF_CTRL1)Bit 4: Disab. Frame Flushing */
#define MFF_ENA_LOOPB (1<<3) /* Bit 3: Enable Loopback */
@@ -1272,61 +1274,61 @@
/* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */
/* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */
- /* Bit 7: reserved */
+ /* Bit 7: reserved */
#define MFF_WSP_T_ON (1<<6) /* Bit 6: (Tx) Write Shadow Pt TestOn */
#define MFF_WSP_T_OFF (1<<5) /* Bit 5: (Tx) Write Shadow Pt TstOff */
-#define MFF_WSP_INC (1<<4) /* Bit 4: (Tx) Write Shadow Pt Increm */
-#define MFF_PC_DEC (1<<3) /* Bit 3: Packet Counter Decrem */
-#define MFF_PC_T_ON (1<<2) /* Bit 2: Packet Counter Test On */
+#define MFF_WSP_INC (1<<4) /* Bit 4: (Tx) Write Shadow Pt Increm */
+#define MFF_PC_DEC (1<<3) /* Bit 3: Packet Counter Decrem */
+#define MFF_PC_T_ON (1<<2) /* Bit 2: Packet Counter Test On */
#define MFF_PC_T_OFF (1<<1) /* Bit 1: Packet Counter Tst Off */
-#define MFF_PC_INC (1<<0) /* Bit 0: Packet Counter Increm */
+#define MFF_PC_INC (1<<0) /* Bit 0: Packet Counter Increm */
/* RX_MFF_TST1 8 bit Receive MAC FIFO Test Register 1 */
/* TX_MFF_TST1 8 bit Transmit MAC FIFO Test Register 1 */
- /* Bit 7: reserved */
-#define MFF_WP_T_ON (1<<6) /* Bit 6: Write Pointer Test On */
+ /* Bit 7: reserved */
+#define MFF_WP_T_ON (1<<6) /* Bit 6: Write Pointer Test On */
#define MFF_WP_T_OFF (1<<5) /* Bit 5: Write Pointer Test Off */
-#define MFF_WP_INC (1<<4) /* Bit 4: Write Pointer Increm */
- /* Bit 3: reserved */
-#define MFF_RP_T_ON (1<<2) /* Bit 2: Read Pointer Test On */
+#define MFF_WP_INC (1<<4) /* Bit 4: Write Pointer Increm */
+ /* Bit 3: reserved */
+#define MFF_RP_T_ON (1<<2) /* Bit 2: Read Pointer Test On */
#define MFF_RP_T_OFF (1<<1) /* Bit 1: Read Pointer Test Off */
-#define MFF_RP_DEC (1<<0) /* Bit 0: Read Pointer Decrement */
+#define MFF_RP_DEC (1<<0) /* Bit 0: Read Pointer Decrement */
/* RX_MFF_CTRL2 8 bit Receive MAC FIFO Control Reg 2 */
/* TX_MFF_CTRL2 8 bit Transmit MAC FIFO Control Reg 2 */
- /* Bit 7..4: reserved */
+ /* Bit 7..4: reserved */
#define MFF_ENA_OP_MD (1<<3) /* Bit 3: Enable Operation Mode */
#define MFF_DIS_OP_MD (1<<2) /* Bit 2: Disab. Operation Mode */
-#define MFF_RST_CLR (1<<1) /* Bit 1: Clear MAC FIFO Reset */
-#define MFF_RST_SET (1<<0) /* Bit 0: Set MAC FIFO Reset */
+#define MFF_RST_CLR (1<<1) /* Bit 1: Clear MAC FIFO Reset */
+#define MFF_RST_SET (1<<0) /* Bit 0: Set MAC FIFO Reset */
/* Receive, Transmit, and Link LED Counter Registers */
-/* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */
-/* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */
-/* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */
- /* Bit 7..3: reserved */
+/* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */
+/* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */
+/* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */
+ /* Bit 7..3: reserved */
#define LED_START (1<<2) /* Bit 2: Start Timer */
#define LED_STOP (1<<1) /* Bit 1: Stop Timer */
#define LED_STATE (1<<0) /* Bit 0:(Rx/Tx)LED State, 1=LED on */
#define LED_CLR_IRQ (1<<0) /* Bit 0:(Lnk) Clear Link IRQ */
-/* RX_LED_TST 8 bit Receive LED Cnt Test Register */
-/* TX_LED_TST 8 bit Transmit LED Cnt Test Register */
-/* LNK_SYNC_TST 8 bit Link Sync Cnt Test Register */
- /* Bit 7..3: reserved */
+/* RX_LED_TST 8 bit Receive LED Cnt Test Register */
+/* TX_LED_TST 8 bit Transmit LED Cnt Test Register */
+/* LNK_SYNC_TST 8 bit Link Sync Cnt Test Register */
+ /* Bit 7..3: reserved */
#define LED_T_ON (1<<2) /* Bit 2: LED Counter Testmode On */
#define LED_T_OFF (1<<1) /* Bit 1: LED Counter Testmode Off */
#define LED_T_STEP (1<<0) /* Bit 0: LED Counter Step */
/* LNK_LED_REG 8 bit Link LED Register */
- /* Bit 7..6: reserved */
-#define LED_BLK_ON (1<<5) /* Bit 5: Link LED Blinking On */
-#define LED_BLK_OFF (1<<4) /* Bit 4: Link LED Blinking Off */
-#define LED_SYNC_ON (1<<3) /* Bit 3: Use Sync Wire to switch LED */
+ /* Bit 7..6: reserved */
+#define LED_BLK_ON (1<<5) /* Bit 5: Link LED Blinking On */
+#define LED_BLK_OFF (1<<4) /* Bit 4: Link LED Blinking Off */
+#define LED_SYNC_ON (1<<3) /* Bit 3: Use Sync Wire to switch LED */
#define LED_SYNC_OFF (1<<2) /* Bit 2: Disable Sync Wire Input */
-#define LED_ON (1<<1) /* Bit 1: switch LED on */
-#define LED_OFF (1<<0) /* Bit 0: switch LED off */
+#define LED_ON (1<<1) /* Bit 1: switch LED on */
+#define LED_OFF (1<<0) /* Bit 0: switch LED off */
/* Receive and Transmit Descriptors ******************************************/
@@ -1334,42 +1336,42 @@
/* Transmit Descriptor struct */
typedef struct s_HwTxd {
SK_U32 volatile TxCtrl; /* Transmit Buffer Control Field */
- SK_U32 TxNext ; /* Physical Address Pointer to the next TxD */
- SK_U32 TxAdrLo ; /* Physical Tx Buffer Address lower dword */
- SK_U32 TxAdrHi ; /* Physical Tx Buffer Address upper dword */
- SK_U32 TxStat ; /* Transmit Frame Status Word */
+ SK_U32 TxNext; /* Physical Address Pointer to the next TxD */
+ SK_U32 TxAdrLo; /* Physical Tx Buffer Address lower dword */
+ SK_U32 TxAdrHi; /* Physical Tx Buffer Address upper dword */
+ SK_U32 TxStat; /* Transmit Frame Status Word */
#ifndef SK_USE_REV_DESC
- SK_U16 TxTcpOffs ; /* TCP Checksum Calculation Start Value */
- SK_U16 TxRes1 ; /* 16 bit reserved field */
- SK_U16 TxTcpWp ; /* TCP Checksum Write Position */
- SK_U16 TxTcpSp ; /* TCP Checksum Calculation Start Position */
+ SK_U16 TxTcpOffs; /* TCP Checksum Calculation Start Value */
+ SK_U16 TxRes1; /* 16 bit reserved field */
+ SK_U16 TxTcpWp; /* TCP Checksum Write Position */
+ SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */
#else /* SK_USE_REV_DESC */
- SK_U16 TxRes1 ; /* 16 bit reserved field */
- SK_U16 TxTcpOffs ; /* TCP Checksum Calculation Start Value */
- SK_U16 TxTcpSp ; /* TCP Checksum Calculation Start Position */
- SK_U16 TxTcpWp ; /* TCP Checksum Write Position */
+ SK_U16 TxRes1; /* 16 bit reserved field */
+ SK_U16 TxTcpOffs; /* TCP Checksum Calculation Start Value */
+ SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */
+ SK_U16 TxTcpWp; /* TCP Checksum Write Position */
#endif /* SK_USE_REV_DESC */
- SK_U32 TxRes2; /* 32 bit reserved field */
+ SK_U32 TxRes2; /* 32 bit reserved field */
} SK_HWTXD;
/* Receive Descriptor struct */
typedef struct s_HwRxd {
SK_U32 volatile RxCtrl; /* Receive Buffer Control Field */
- SK_U32 RxNext ; /* Physical Address Pointer to the next TxD */
- SK_U32 RxAdrLo ; /* Physical Receive Buffer Address lower dword*/
- SK_U32 RxAdrHi ; /* Physical Receive Buffer Address upper dword*/
- SK_U32 RxStat ; /* Receive Frame Status Word */
- SK_U32 RxTiSt ; /* Receive Timestamp provided by the XMAC */
+ SK_U32 RxNext; /* Physical Address Pointer to the next TxD */
+ SK_U32 RxAdrLo; /* Physical Receive Buffer Address lower dword*/
+ SK_U32 RxAdrHi; /* Physical Receive Buffer Address upper dword*/
+ SK_U32 RxStat; /* Receive Frame Status Word */
+ SK_U32 RxTiSt; /* Receive Timestamp provided by the XMAC */
#ifndef SK_USE_REV_DESC
- SK_U16 RxTcpSum1 ; /* TCP Checksum 1 */
- SK_U16 RxTcpSum2 ; /* TCP Checksum 2 */
- SK_U16 RxTcpSp1 ; /* TCP Checksum Calculation Start Position 1 */
- SK_U16 RxTcpSp2 ; /* TCP Checksum Calculation Start Position 2 */
+ SK_U16 RxTcpSum1; /* TCP Checksum 1 */
+ SK_U16 RxTcpSum2; /* TCP Checksum 2 */
+ SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */
+ SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */
#else /* SK_USE_REV_DESC */
- SK_U16 RxTcpSum2 ; /* TCP Checksum 2 */
- SK_U16 RxTcpSum1 ; /* TCP Checksum 1 */
- SK_U16 RxTcpSp2 ; /* TCP Checksum Calculation Start Position 2 */
- SK_U16 RxTcpSp1 ; /* TCP Checksum Calculation Start Position 1 */
+ SK_U16 RxTcpSum2; /* TCP Checksum 2 */
+ SK_U16 RxTcpSum1; /* TCP Checksum 1 */
+ SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */
+ SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */
#endif /* SK_USE_REV_DESC */
} SK_HWRXD;
@@ -1387,23 +1389,23 @@
/* Descriptor Bit Definition */
/* TxCtrl Transmit Buffer Control Field */
/* RxCtrl Receive Buffer Control Field */
-#define BMU_OWN (1UL<<31) /* Bit 31: OWN bit: 0=host/1=BMU */
-#define BMU_STF (1L<<30) /* Bit 30: Start of Frame ? */
-#define BMU_EOF (1L<<29) /* Bit 29: End of Frame ? */
-#define BMU_IRQ_EOB (1L<<28) /* Bit 28: Req "End of Buff" IRQ */
-#define BMU_IRQ_EOF (1L<<27) /* Bit 27: Req "End of Frame" IRQ*/
+#define BMU_OWN (1UL<<31) /* Bit 31: OWN bit: 0=host/1=BMU */
+#define BMU_STF (1L<<30) /* Bit 30: Start of Frame ? */
+#define BMU_EOF (1L<<29) /* Bit 29: End of Frame ? */
+#define BMU_IRQ_EOB (1L<<28) /* Bit 28: Req "End of Buff" IRQ */
+#define BMU_IRQ_EOF (1L<<27) /* Bit 27: Req "End of Frame" IRQ*/
/* TxCtrl specific bits */
-#define BMU_STFWD (1L<<26) /* Bit 26: (Tx) Store&Forward Frame */
-#define BMU_NO_FCS (1L<<25) /* Bit 25: (Tx) disable XMAC FCS gener*/
-#define BMU_SW (1L<<24) /* Bit 24: (Tx) 1 bit res. for SW use */
+#define BMU_STFWD (1L<<26) /* Bit 26: (Tx) Store&Forward Frame */
+#define BMU_NO_FCS (1L<<25) /* Bit 25: (Tx) disable XMAC FCS gener*/
+#define BMU_SW (1L<<24) /* Bit 24: (Tx) 1 bit res. for SW use */
/* RxCtrl specific bits */
-#define BMU_DEV_0 (1L<<26) /* Bit 26: (Rx) transfer data to Dev0 */
+#define BMU_DEV_0 (1L<<26) /* Bit 26: (Rx) transfer data to Dev0 */
#define BMU_STAT_VAL (1L<<25) /* Bit 25: (Rx) RxStat Valid */
#define BMU_TIST_VAL (1L<<24) /* Bit 24: (Rx) RxTiSt Valid */
- /* Bit 23..16: BMU Check Opcodes */
-#define BMU_CHECK 0x00550000L /* Default BMU check */
+ /* Bit 23..16: BMU Check Opcodes */
+#define BMU_CHECK 0x00550000L /* Default BMU check */
#define BMU_TCP_CHECK 0x00560000L /* Descr with TCP ext */
-#define BMU_BBC 0x0000FFFFL /* Bit 15..0: Buffer Byte Counter */
+#define BMU_BBC 0x0000FFFFL /* Bit 15..0: Buffer Byte Counter */
/* TxStat Transmit Frame Status Word */
/* RxStat Receive Frame Status Word */
@@ -1420,8 +1422,8 @@
* FlashProm specification
*/
#define MAX_PAGES 0x20000L /* Every byte has a single page */
-#define MAX_FADDR 1 /* 1 byte per page */
-#define SKFDDI_PSZ 8 /* address PROM size */
+#define MAX_FADDR 1 /* 1 byte per page */
+#define SKFDDI_PSZ 8 /* address PROM size */
/* macros ********************************************************************/
@@ -1507,7 +1509,7 @@
* (p)Val Value or pointer to the value which should be read or
* written.
*
- * usage: XM_OUT16(IoC, MAC_1, XM_MMU_CMD, Value) ;
+ * usage: XM_OUT16(IoC, MAC_1, XM_MMU_CMD, Value);
*/
#ifdef SK_LITTLE_ENDIAN
@@ -1520,19 +1522,19 @@
#define XMA(Mac,Reg) (((0x1000 << (Mac)) + 0x1000) | ((Reg) << 1))
-#define XM_IN16(IoC,Mac,Reg,pVal) SK_IN16((IoC),XMA((Mac),(Reg)),(pVal))
-#define XM_OUT16(IoC,Mac,Reg,Val) SK_OUT16((IoC),XMA((Mac),(Reg)),(Val))
+#define XM_IN16(IoC,Mac,Reg,pVal) SK_IN16((IoC), XMA((Mac), (Reg)), (pVal))
+#define XM_OUT16(IoC,Mac,Reg,Val) SK_OUT16((IoC), XMA((Mac), (Reg)), (Val))
-#define XM_IN32(IoC,Mac,Reg,pVal) { \
- SK_IN16((IoC),XMA((Mac),(Reg)), \
+#define XM_IN32(IoC,Mac,Reg,pVal) { \
+ SK_IN16((IoC), XMA((Mac), (Reg)), \
(SK_U16 *)&((SK_U16 *)(pVal))[XM_WORD_LO]); \
- SK_IN16((IoC),XMA((Mac),(Reg+2)), \
+ SK_IN16((IoC), XMA((Mac), (Reg+2)), \
(SK_U16 *)&((SK_U16 *)(pVal))[XM_WORD_HI]); \
}
-#define XM_OUT32(IoC,Mac,Reg,Val) { \
- SK_OUT16((IoC),XMA((Mac),(Reg)), (SK_U16)((Val) & 0x0000ffffL));\
- SK_OUT16((IoC),XMA((Mac),(Reg+2)),(SK_U16)(((Val)>>16) & 0x0000ffffL));\
+#define XM_OUT32(IoC,Mac,Reg,Val) { \
+ SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16)((Val) & 0x0000ffffL)); \
+ SK_OUT16((IoC), XMA((Mac), (Reg+2)),(SK_U16)(((Val)>>16) & 0x0000ffffL)); \
}
/*
@@ -1540,67 +1542,67 @@
*/
#define XM_INADDR(IoC, Mac, Reg, pVal) { \
- SK_U16 Word; \
- SK_U8 *pByte; \
+ SK_U16 Word; \
+ SK_U8 *pByte; \
pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \
SK_IN16((IoC), XMA((Mac), (Reg)), &Word); \
- pByte[0] = (SK_U8) (Word & 0x00ff); \
- pByte[1] = (SK_U8) ((Word >> 8) & 0x00ff); \
+ pByte[0] = (SK_U8)(Word & 0x00ff); \
+ pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \
SK_IN16((IoC), XMA((Mac), (Reg+2)), &Word); \
- pByte[2] = (SK_U8) (Word & 0x00ff); \
- pByte[3] = (SK_U8) ((Word >> 8) & 0x00ff); \
+ pByte[2] = (SK_U8)(Word & 0x00ff); \
+ pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \
SK_IN16((IoC), XMA((Mac), (Reg+4)), &Word); \
- pByte[4] = (SK_U8) (Word & 0x00ff); \
- pByte[5] = (SK_U8) ((Word >> 8) & 0x00ff); \
+ pByte[4] = (SK_U8)(Word & 0x00ff); \
+ pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \
}
#define XM_OUTADDR(IoC, Mac, Reg, pVal) { \
- SK_U8 *pByte; \
+ SK_U8 *pByte; \
pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \
SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16) \
- (((SK_U16)(pByte[0]) & 0x00ff)| \
- (((SK_U16)(pByte[1]) << 8) & 0xff00))); \
- SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16) \
- (((SK_U16)(pByte[2]) & 0x00ff)| \
- (((SK_U16)(pByte[3]) << 8) & 0xff00))); \
- SK_OUT16((IoC), XMA((Mac), (Reg+4)), (SK_U16) \
- (((SK_U16)(pByte[4]) & 0x00ff)| \
- (((SK_U16)(pByte[5]) << 8) & 0xff00))); \
+ (((SK_U16)(pByte[0]) & 0x00ff) | \
+ (((SK_U16)(pByte[1]) << 8) & 0xff00))); \
+ SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16) \
+ (((SK_U16)(pByte[2]) & 0x00ff) | \
+ (((SK_U16)(pByte[3]) << 8) & 0xff00))); \
+ SK_OUT16((IoC), XMA((Mac), (Reg+4)), (SK_U16) \
+ (((SK_U16)(pByte[4]) & 0x00ff) | \
+ (((SK_U16)(pByte[5]) << 8) & 0xff00))); \
}
#define XM_INHASH(IoC, Mac, Reg, pVal) { \
- SK_U16 Word; \
- SK_U8 *pByte; \
+ SK_U16 Word; \
+ SK_U8 *pByte; \
pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \
SK_IN16((IoC), XMA((Mac), (Reg)), &Word); \
- pByte[0] = (SK_U8) (Word & 0x00ff); \
- pByte[1] = (SK_U8) ((Word >> 8) & 0x00ff); \
+ pByte[0] = (SK_U8)(Word & 0x00ff); \
+ pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \
SK_IN16((IoC), XMA((Mac), (Reg+2)), &Word); \
- pByte[2] = (SK_U8) (Word & 0x00ff); \
- pByte[3] = (SK_U8) ((Word >> 8) & 0x00ff); \
+ pByte[2] = (SK_U8)(Word & 0x00ff); \
+ pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \
SK_IN16((IoC), XMA((Mac), (Reg+4)), &Word); \
- pByte[4] = (SK_U8) (Word & 0x00ff); \
- pByte[5] = (SK_U8) ((Word >> 8) & 0x00ff); \
+ pByte[4] = (SK_U8)(Word & 0x00ff); \
+ pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \
SK_IN16((IoC), XMA((Mac), (Reg+6)), &Word); \
- pByte[6] = (SK_U8) (Word & 0x00ff); \
- pByte[7] = (SK_U8) ((Word >> 8) & 0x00ff); \
+ pByte[6] = (SK_U8)(Word & 0x00ff); \
+ pByte[7] = (SK_U8)((Word >> 8) & 0x00ff); \
}
#define XM_OUTHASH(IoC, Mac, Reg, pVal) { \
- SK_U8 *pByte; \
+ SK_U8 *pByte; \
pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \
SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16) \
- (((SK_U16)(pByte[0]) & 0x00ff)| \
- (((SK_U16)(pByte[1]) << 8) & 0xff00))); \
- SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16) \
- (((SK_U16)(pByte[2]) & 0x00ff)| \
- (((SK_U16)(pByte[3]) << 8) & 0xff00))); \
- SK_OUT16((IoC), XMA((Mac), (Reg+4)), (SK_U16) \
- (((SK_U16)(pByte[4]) & 0x00ff)| \
- (((SK_U16)(pByte[5]) << 8) & 0xff00))); \
- SK_OUT16((IoC), XMA((Mac), (Reg+6)), (SK_U16) \
- (((SK_U16)(pByte[6]) & 0x00ff)| \
- (((SK_U16)(pByte[7]) << 8) & 0xff00))); \
+ (((SK_U16)(pByte[0]) & 0x00ff)| \
+ (((SK_U16)(pByte[1]) << 8) & 0xff00))); \
+ SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16) \
+ (((SK_U16)(pByte[2]) & 0x00ff)| \
+ (((SK_U16)(pByte[3]) << 8) & 0xff00))); \
+ SK_OUT16((IoC), XMA((Mac), (Reg+4)), (SK_U16) \
+ (((SK_U16)(pByte[4]) & 0x00ff)| \
+ (((SK_U16)(pByte[5]) << 8) & 0xff00))); \
+ SK_OUT16((IoC), XMA((Mac), (Reg+6)), (SK_U16) \
+ (((SK_U16)(pByte[6]) & 0x00ff)| \
+ (((SK_U16)(pByte[7]) << 8) & 0xff00))); \
}
/*
@@ -1637,56 +1639,56 @@
* comes back. This is checked in DEBUG mode.
*/
#ifndef DEBUG
-#define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) { \
- SK_U16 Mmu; \
- \
- XM_OUT16((IoC),(Mac), XM_PHY_ADDR, (PhyReg)|(pPort)->PhyAddr); \
- XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
- if ((pPort)->PhyType != SK_PHY_XMAC) { \
- do { \
- XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
- } while ((Mmu & XM_MMU_PHY_RDY) == 0); \
- XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
- } \
+#define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) { \
+ SK_U16 Mmu; \
+ \
+ XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \
+ XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
+ if ((pPort)->PhyType != SK_PHY_XMAC) { \
+ do { \
+ XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
+ } while ((Mmu & XM_MMU_PHY_RDY) == 0); \
+ XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
+ } \
}
#else
-#define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) { \
- SK_U16 Mmu; \
- int __i = 0; \
- \
- XM_OUT16((IoC),(Mac), XM_PHY_ADDR, (PhyReg)|(pPort)->PhyAddr); \
- XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
- if ((pPort)->PhyType != SK_PHY_XMAC) { \
- do { \
- XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
- __i++; \
- if (__i > 10000) { \
- SK_DBG_PRINTF("*****************************\n"); \
- SK_DBG_PRINTF("PHY_READ on uninitialized PHY\n"); \
- SK_DBG_PRINTF("*****************************\n"); \
- break; \
- } \
- } while ((Mmu & XM_MMU_PHY_RDY) == 0); \
- XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
- } \
+#define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) { \
+ SK_U16 Mmu; \
+ int __i = 0; \
+ \
+ XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \
+ XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
+ if ((pPort)->PhyType != SK_PHY_XMAC) { \
+ do { \
+ XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
+ __i++; \
+ if (__i > 100000) { \
+ SK_DBG_PRINTF("*****************************\n"); \
+ SK_DBG_PRINTF("PHY_READ on uninitialized PHY\n"); \
+ SK_DBG_PRINTF("*****************************\n"); \
+ break; \
+ } \
+ } while ((Mmu & XM_MMU_PHY_RDY) == 0); \
+ XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
+ } \
}
#endif
-#define PHY_WRITE(IoC, pPort, Mac, PhyReg, Val) { \
- SK_U16 Mmu; \
- \
- if ((pPort)->PhyType != SK_PHY_XMAC) { \
- do { \
- XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
- } while ((Mmu & XM_MMU_PHY_BUSY) != 0); \
- } \
- XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg)|(pPort)->PhyAddr); \
- XM_OUT16((IoC), (Mac), XM_PHY_DATA, (Val)); \
- if ((pPort)->PhyType != SK_PHY_XMAC) { \
- do { \
- XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
- } while ((Mmu & XM_MMU_PHY_BUSY) != 0); \
- } \
+#define PHY_WRITE(IoC, pPort, Mac, PhyReg, Val) { \
+ SK_U16 Mmu; \
+ \
+ if ((pPort)->PhyType != SK_PHY_XMAC) { \
+ do { \
+ XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
+ } while ((Mmu & XM_MMU_PHY_BUSY) != 0); \
+ } \
+ XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \
+ XM_OUT16((IoC), (Mac), XM_PHY_DATA, (Val)); \
+ if ((pPort)->PhyType != SK_PHY_XMAC) { \
+ do { \
+ XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
+ } while ((Mmu & XM_MMU_PHY_BUSY) != 0); \
+ } \
}
/*
@@ -1731,7 +1733,7 @@
* Mode Mode to set for this LED
*/
#define SK_HWAC_LINK_LED(pAC, IoC, Port, Mode) \
-SK_OUT8(IoC, MR_ADDR(Port,LNK_LED_REG), Mode);
+ SK_OUT8(IoC, MR_ADDR(Port,LNK_LED_REG), Mode);
/* typedefs *******************************************************************/
FUNET's LINUX-ADM group, linux-adm@nic.funet.fi
TCL-scripts by Sam Shen (who was at: slshen@lbl.gov)