patch-2.4.22 linux-2.4.22/arch/mips/dec/setup.c
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- Lines: 668
- Date:
2003-08-25 04:44:39.000000000 -0700
- Orig file:
linux-2.4.21/arch/mips/dec/setup.c
- Orig date:
2002-11-28 15:53:10.000000000 -0800
diff -urN linux-2.4.21/arch/mips/dec/setup.c linux-2.4.22/arch/mips/dec/setup.c
@@ -6,7 +6,7 @@
* for more details.
*
* Copyright (C) 1998 Harald Koerfgen
- * Copyright (C) 2000, 2001, 2002 Maciej W. Rozycki
+ * Copyright (C) 2000, 2001, 2002, 2003 Maciej W. Rozycki
*/
#include <linux/config.h>
#include <linux/sched.h>
@@ -16,6 +16,7 @@
#include <linux/console.h>
#include <linux/init.h>
#include <linux/module.h>
+#include <linux/spinlock.h>
#include <linux/types.h>
#include <asm/cpu.h>
@@ -24,19 +25,20 @@
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <asm/reboot.h>
+#include <asm/time.h>
#include <asm/traps.h>
#include <asm/wbflush.h>
#include <asm/dec/interrupts.h>
+#include <asm/dec/ioasic.h>
+#include <asm/dec/ioasic_addrs.h>
+#include <asm/dec/ioasic_ints.h>
#include <asm/dec/kn01.h>
#include <asm/dec/kn02.h>
#include <asm/dec/kn02ba.h>
#include <asm/dec/kn02ca.h>
#include <asm/dec/kn03.h>
#include <asm/dec/kn230.h>
-#include <asm/dec/ioasic.h>
-#include <asm/dec/ioasic_addrs.h>
-#include <asm/dec/ioasic_ints.h>
extern void dec_machine_restart(char *command);
@@ -46,6 +48,8 @@
extern asmlinkage void decstation_handle_int(void);
+spinlock_t ioasic_ssr_lock;
+
volatile u32 *ioasic_base;
unsigned long dec_kn_slot_size;
@@ -75,53 +79,61 @@
[0 ... DEC_NR_INTS - 1] = -1
};
int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = {
- { { i: ~0 }, { p: dec_intr_unimplemented } },
+ { { .i = ~0 }, { .p = dec_intr_unimplemented } },
};
int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2] = {
- { { i: ~0 }, { p: asic_intr_unimplemented } },
+ { { .i = ~0 }, { .p = asic_intr_unimplemented } },
};
int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU);
-static struct irqaction ioirq = {NULL, 0, 0, "cascade", NULL, NULL};
-static struct irqaction fpuirq = {NULL, 0, 0, "fpu", NULL, NULL};
-
-static struct irqaction haltirq = {dec_intr_halt, 0, 0, "halt", NULL, NULL};
+static struct irqaction ioirq = {
+ .handler = no_action,
+ .name = "cascade",
+};
+static struct irqaction fpuirq = {
+ .handler = no_action,
+ .name = "fpu",
+};
+static struct irqaction busirq = {
+ .flags = SA_INTERRUPT,
+ .name = "bus error",
+};
-void (*board_time_init) (struct irqaction * irq);
+static struct irqaction haltirq = {
+ .handler = dec_intr_halt,
+ .name = "halt",
+};
/*
- * enable the periodic interrupts
+ * Bus error (DBE/IBE exceptions and bus interrupts) handling setup.
*/
-static void __init dec_time_init(struct irqaction *irq)
+void __init dec_be_init(void)
{
- /*
- * Here we go, enable periodic rtc interrupts.
- */
-
-#ifndef LOG_2_HZ
-# define LOG_2_HZ 7
-#endif
-
- CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - LOG_2_HZ), RTC_REG_A);
- CMOS_WRITE(CMOS_READ(RTC_REG_B) | RTC_PIE, RTC_REG_B);
- setup_irq(dec_interrupt[DEC_IRQ_RTC], irq);
+ switch (mips_machtype) {
+ case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */
+ busirq.flags |= SA_SHIRQ;
+ break;
+ case MACH_DS5000_200: /* DS5000/200 3max */
+ case MACH_DS5000_2X0: /* DS5000/240 3max+ */
+ case MACH_DS5900: /* DS5900 bigmax */
+ board_be_handler = dec_ecc_be_handler;
+ busirq.handler = dec_ecc_be_interrupt;
+ dec_ecc_be_init();
+ break;
+ }
}
-/*
- * Bus error (DBE/IBE exceptions and memory interrupts) handling
- * setup. Nothing for now.
- */
-void __init bus_error_init(void)
-{
-}
-
+extern void dec_time_init(void);
+extern void dec_timer_setup(struct irqaction *);
void __init decstation_setup(void)
{
+ board_be_init = dec_be_init;
board_time_init = dec_time_init;
+ board_timer_setup = dec_timer_setup;
wbflush_setup();
@@ -152,7 +164,7 @@
[DEC_IRQ_HALT] = -1,
[DEC_IRQ_ISDN] = -1,
[DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE),
- [DEC_IRQ_MEMORY] = DEC_CPU_IRQ_NR(KN01_CPU_INR_MEMORY),
+ [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS),
[DEC_IRQ_PSU] = -1,
[DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC),
[DEC_IRQ_SCC0] = -1,
@@ -175,10 +187,10 @@
[DEC_IRQ_SCC0A_RXDMA] = -1,
[DEC_IRQ_SCC0A_TXERR] = -1,
[DEC_IRQ_SCC0A_TXDMA] = -1,
- [DEC_IRQ_SCC0B_RXERR] = -1,
- [DEC_IRQ_SCC0B_RXDMA] = -1,
- [DEC_IRQ_SCC0B_TXERR] = -1,
- [DEC_IRQ_SCC0B_TXDMA] = -1,
+ [DEC_IRQ_AB_RXERR] = -1,
+ [DEC_IRQ_AB_RXDMA] = -1,
+ [DEC_IRQ_AB_TXERR] = -1,
+ [DEC_IRQ_AB_TXDMA] = -1,
[DEC_IRQ_SCC1A_RXERR] = -1,
[DEC_IRQ_SCC1A_RXDMA] = -1,
[DEC_IRQ_SCC1A_TXERR] = -1,
@@ -186,26 +198,22 @@
};
static int_ptr kn01_cpu_mask_nr_tbl[][2] __initdata = {
- { { i: DEC_CPU_IRQ_MASK(KN01_CPU_INR_MEMORY) },
- { i: DEC_CPU_IRQ_NR(KN01_CPU_INR_MEMORY) } },
- { { i: DEC_CPU_IRQ_MASK(KN01_CPU_INR_RTC) },
- { i: DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC) } },
- { { i: DEC_CPU_IRQ_MASK(KN01_CPU_INR_DZ11) },
- { i: DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11) } },
- { { i: DEC_CPU_IRQ_MASK(KN01_CPU_INR_SII) },
- { i: DEC_CPU_IRQ_NR(KN01_CPU_INR_SII) } },
- { { i: DEC_CPU_IRQ_MASK(KN01_CPU_INR_LANCE) },
- { i: DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE) } },
- { { i: DEC_CPU_IRQ_ALL },
- { p: cpu_all_int } },
+ { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_BUS) },
+ { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS) } },
+ { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_RTC) },
+ { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC) } },
+ { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_DZ11) },
+ { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11) } },
+ { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_SII) },
+ { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII) } },
+ { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_LANCE) },
+ { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE) } },
+ { { .i = DEC_CPU_IRQ_ALL },
+ { .p = cpu_all_int } },
};
void __init dec_init_kn01(void)
{
- /* Setup some memory addresses. */
- dec_rtc_base = (void *)KN01_RTC_BASE;
- dec_kn_slot_size = KN01_SLOT_SIZE;
-
/* IRQ routing. */
memcpy(&dec_interrupt, &kn01_interrupt,
sizeof(kn01_interrupt));
@@ -233,7 +241,7 @@
[DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN230_CPU_INR_HALT),
[DEC_IRQ_ISDN] = -1,
[DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN230_CPU_INR_LANCE),
- [DEC_IRQ_MEMORY] = DEC_CPU_IRQ_NR(KN230_CPU_INR_MEMORY),
+ [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS),
[DEC_IRQ_PSU] = -1,
[DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC),
[DEC_IRQ_SCC0] = -1,
@@ -256,10 +264,10 @@
[DEC_IRQ_SCC0A_RXDMA] = -1,
[DEC_IRQ_SCC0A_TXERR] = -1,
[DEC_IRQ_SCC0A_TXDMA] = -1,
- [DEC_IRQ_SCC0B_RXERR] = -1,
- [DEC_IRQ_SCC0B_RXDMA] = -1,
- [DEC_IRQ_SCC0B_TXERR] = -1,
- [DEC_IRQ_SCC0B_TXDMA] = -1,
+ [DEC_IRQ_AB_RXERR] = -1,
+ [DEC_IRQ_AB_RXDMA] = -1,
+ [DEC_IRQ_AB_TXERR] = -1,
+ [DEC_IRQ_AB_TXDMA] = -1,
[DEC_IRQ_SCC1A_RXERR] = -1,
[DEC_IRQ_SCC1A_RXDMA] = -1,
[DEC_IRQ_SCC1A_TXERR] = -1,
@@ -267,24 +275,20 @@
};
static int_ptr kn230_cpu_mask_nr_tbl[][2] __initdata = {
- { { i: DEC_CPU_IRQ_MASK(KN230_CPU_INR_MEMORY) },
- { i: DEC_CPU_IRQ_NR(KN230_CPU_INR_MEMORY) } },
- { { i: DEC_CPU_IRQ_MASK(KN230_CPU_INR_RTC) },
- { i: DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC) } },
- { { i: DEC_CPU_IRQ_MASK(KN230_CPU_INR_DZ11) },
- { i: DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11) } },
- { { i: DEC_CPU_IRQ_MASK(KN230_CPU_INR_SII) },
- { i: DEC_CPU_IRQ_NR(KN230_CPU_INR_SII) } },
- { { i: DEC_CPU_IRQ_ALL },
- { p: cpu_all_int } },
+ { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_BUS) },
+ { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS) } },
+ { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_RTC) },
+ { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC) } },
+ { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_DZ11) },
+ { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11) } },
+ { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_SII) },
+ { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII) } },
+ { { .i = DEC_CPU_IRQ_ALL },
+ { .p = cpu_all_int } },
};
void __init dec_init_kn230(void)
{
- /* Setup some memory addresses. */
- dec_rtc_base = (void *)KN01_RTC_BASE;
- dec_kn_slot_size = KN01_SLOT_SIZE;
-
/* IRQ routing. */
memcpy(&dec_interrupt, &kn230_interrupt,
sizeof(kn230_interrupt));
@@ -312,7 +316,7 @@
[DEC_IRQ_HALT] = -1,
[DEC_IRQ_ISDN] = -1,
[DEC_IRQ_LANCE] = KN02_IRQ_NR(KN02_CSR_INR_LANCE),
- [DEC_IRQ_MEMORY] = DEC_CPU_IRQ_NR(KN02_CPU_INR_MEMORY),
+ [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS),
[DEC_IRQ_PSU] = -1,
[DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC),
[DEC_IRQ_SCC0] = -1,
@@ -335,10 +339,10 @@
[DEC_IRQ_SCC0A_RXDMA] = -1,
[DEC_IRQ_SCC0A_TXERR] = -1,
[DEC_IRQ_SCC0A_TXDMA] = -1,
- [DEC_IRQ_SCC0B_RXERR] = -1,
- [DEC_IRQ_SCC0B_RXDMA] = -1,
- [DEC_IRQ_SCC0B_TXERR] = -1,
- [DEC_IRQ_SCC0B_TXDMA] = -1,
+ [DEC_IRQ_AB_RXERR] = -1,
+ [DEC_IRQ_AB_RXDMA] = -1,
+ [DEC_IRQ_AB_TXERR] = -1,
+ [DEC_IRQ_AB_TXDMA] = -1,
[DEC_IRQ_SCC1A_RXERR] = -1,
[DEC_IRQ_SCC1A_RXDMA] = -1,
[DEC_IRQ_SCC1A_TXERR] = -1,
@@ -346,39 +350,35 @@
};
static int_ptr kn02_cpu_mask_nr_tbl[][2] __initdata = {
- { { i: DEC_CPU_IRQ_MASK(KN02_CPU_INR_MEMORY) },
- { i: DEC_CPU_IRQ_NR(KN02_CPU_INR_MEMORY) } },
- { { i: DEC_CPU_IRQ_MASK(KN02_CPU_INR_RTC) },
- { i: DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC) } },
- { { i: DEC_CPU_IRQ_MASK(KN02_CPU_INR_CASCADE) },
- { p: kn02_io_int } },
- { { i: DEC_CPU_IRQ_ALL },
- { p: cpu_all_int } },
+ { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_BUS) },
+ { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS) } },
+ { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_RTC) },
+ { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC) } },
+ { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_CASCADE) },
+ { .p = kn02_io_int } },
+ { { .i = DEC_CPU_IRQ_ALL },
+ { .p = cpu_all_int } },
};
static int_ptr kn02_asic_mask_nr_tbl[][2] __initdata = {
- { { i: KN02_IRQ_MASK(KN02_CSR_INR_DZ11) },
- { i: KN02_IRQ_NR(KN02_CSR_INR_DZ11) } },
- { { i: KN02_IRQ_MASK(KN02_CSR_INR_ASC) },
- { i: KN02_IRQ_NR(KN02_CSR_INR_ASC) } },
- { { i: KN02_IRQ_MASK(KN02_CSR_INR_LANCE) },
- { i: KN02_IRQ_NR(KN02_CSR_INR_LANCE) } },
- { { i: KN02_IRQ_MASK(KN02_CSR_INR_TC2) },
- { i: KN02_IRQ_NR(KN02_CSR_INR_TC2) } },
- { { i: KN02_IRQ_MASK(KN02_CSR_INR_TC1) },
- { i: KN02_IRQ_NR(KN02_CSR_INR_TC1) } },
- { { i: KN02_IRQ_MASK(KN02_CSR_INR_TC0) },
- { i: KN02_IRQ_NR(KN02_CSR_INR_TC0) } },
- { { i: KN02_IRQ_ALL },
- { p: kn02_all_int } },
+ { { .i = KN02_IRQ_MASK(KN02_CSR_INR_DZ11) },
+ { .i = KN02_IRQ_NR(KN02_CSR_INR_DZ11) } },
+ { { .i = KN02_IRQ_MASK(KN02_CSR_INR_ASC) },
+ { .i = KN02_IRQ_NR(KN02_CSR_INR_ASC) } },
+ { { .i = KN02_IRQ_MASK(KN02_CSR_INR_LANCE) },
+ { .i = KN02_IRQ_NR(KN02_CSR_INR_LANCE) } },
+ { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC2) },
+ { .i = KN02_IRQ_NR(KN02_CSR_INR_TC2) } },
+ { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC1) },
+ { .i = KN02_IRQ_NR(KN02_CSR_INR_TC1) } },
+ { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC0) },
+ { .i = KN02_IRQ_NR(KN02_CSR_INR_TC0) } },
+ { { .i = KN02_IRQ_ALL },
+ { .p = kn02_all_int } },
};
void __init dec_init_kn02(void)
{
- /* Setup some memory addresses. */
- dec_rtc_base = (void *)KN02_RTC_BASE;
- dec_kn_slot_size = KN02_SLOT_SIZE;
-
/* IRQ routing. */
memcpy(&dec_interrupt, &kn02_interrupt,
sizeof(kn02_interrupt));
@@ -413,7 +413,7 @@
[DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_HALT),
[DEC_IRQ_ISDN] = -1,
[DEC_IRQ_LANCE] = IO_IRQ_NR(KN02BA_IO_INR_LANCE),
- [DEC_IRQ_MEMORY] = IO_IRQ_NR(KN02BA_IO_INR_MEMORY),
+ [DEC_IRQ_BUS] = IO_IRQ_NR(KN02BA_IO_INR_BUS),
[DEC_IRQ_PSU] = IO_IRQ_NR(KN02BA_IO_INR_PSU),
[DEC_IRQ_RTC] = IO_IRQ_NR(KN02BA_IO_INR_RTC),
[DEC_IRQ_SCC0] = IO_IRQ_NR(KN02BA_IO_INR_SCC0),
@@ -436,10 +436,10 @@
[DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
[DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
[DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
- [DEC_IRQ_SCC0B_RXERR] = -1,
- [DEC_IRQ_SCC0B_RXDMA] = -1,
- [DEC_IRQ_SCC0B_TXERR] = -1,
- [DEC_IRQ_SCC0B_TXDMA] = -1,
+ [DEC_IRQ_AB_RXERR] = -1,
+ [DEC_IRQ_AB_RXDMA] = -1,
+ [DEC_IRQ_AB_TXERR] = -1,
+ [DEC_IRQ_AB_TXDMA] = -1,
[DEC_IRQ_SCC1A_RXERR] = IO_IRQ_NR(IO_INR_SCC1A_RXERR),
[DEC_IRQ_SCC1A_RXDMA] = IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
[DEC_IRQ_SCC1A_TXERR] = IO_IRQ_NR(IO_INR_SCC1A_TXERR),
@@ -447,44 +447,39 @@
};
static int_ptr kn02ba_cpu_mask_nr_tbl[][2] __initdata = {
- { { i: DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_CASCADE) },
- { p: kn02xa_io_int } },
- { { i: DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC2) },
- { i: DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2) } },
- { { i: DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC1) },
- { i: DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1) } },
- { { i: DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC0) },
- { i: DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0) } },
- { { i: DEC_CPU_IRQ_ALL },
- { p: cpu_all_int } },
+ { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_CASCADE) },
+ { .p = kn02xa_io_int } },
+ { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC2) },
+ { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2) } },
+ { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC1) },
+ { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1) } },
+ { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC0) },
+ { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0) } },
+ { { .i = DEC_CPU_IRQ_ALL },
+ { .p = cpu_all_int } },
};
static int_ptr kn02ba_asic_mask_nr_tbl[][2] __initdata = {
- { { i: IO_IRQ_MASK(KN02BA_IO_INR_MEMORY) },
- { i: IO_IRQ_NR(KN02BA_IO_INR_MEMORY) } },
- { { i: IO_IRQ_MASK(KN02BA_IO_INR_RTC) },
- { i: IO_IRQ_NR(KN02BA_IO_INR_RTC) } },
- { { i: IO_IRQ_DMA },
- { p: asic_dma_int } },
- { { i: IO_IRQ_MASK(KN02BA_IO_INR_SCC0) },
- { i: IO_IRQ_NR(KN02BA_IO_INR_SCC0) } },
- { { i: IO_IRQ_MASK(KN02BA_IO_INR_SCC1) },
- { i: IO_IRQ_NR(KN02BA_IO_INR_SCC1) } },
- { { i: IO_IRQ_MASK(KN02BA_IO_INR_ASC) },
- { i: IO_IRQ_NR(KN02BA_IO_INR_ASC) } },
- { { i: IO_IRQ_MASK(KN02BA_IO_INR_LANCE) },
- { i: IO_IRQ_NR(KN02BA_IO_INR_LANCE) } },
- { { i: IO_IRQ_ALL },
- { p: asic_all_int } },
+ { { .i = IO_IRQ_MASK(KN02BA_IO_INR_BUS) },
+ { .i = IO_IRQ_NR(KN02BA_IO_INR_BUS) } },
+ { { .i = IO_IRQ_MASK(KN02BA_IO_INR_RTC) },
+ { .i = IO_IRQ_NR(KN02BA_IO_INR_RTC) } },
+ { { .i = IO_IRQ_DMA },
+ { .p = asic_dma_int } },
+ { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC0) },
+ { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC0) } },
+ { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC1) },
+ { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC1) } },
+ { { .i = IO_IRQ_MASK(KN02BA_IO_INR_ASC) },
+ { .i = IO_IRQ_NR(KN02BA_IO_INR_ASC) } },
+ { { .i = IO_IRQ_MASK(KN02BA_IO_INR_LANCE) },
+ { .i = IO_IRQ_NR(KN02BA_IO_INR_LANCE) } },
+ { { .i = IO_IRQ_ALL },
+ { .p = asic_all_int } },
};
void __init dec_init_kn02ba(void)
{
- /* Setup some memory addresses. */
- ioasic_base = (void *)KN02BA_IOASIC_BASE;
- dec_rtc_base = (void *)KN02BA_RTC_BASE;
- dec_kn_slot_size = IOASIC_SLOT_SIZE;
-
/* IRQ routing. */
memcpy(&dec_interrupt, &kn02ba_interrupt,
sizeof(kn02ba_interrupt));
@@ -519,7 +514,7 @@
[DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_HALT),
[DEC_IRQ_ISDN] = IO_IRQ_NR(KN02CA_IO_INR_ISDN),
[DEC_IRQ_LANCE] = IO_IRQ_NR(KN02CA_IO_INR_LANCE),
- [DEC_IRQ_MEMORY] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_MEMORY),
+ [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS),
[DEC_IRQ_PSU] = -1,
[DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC),
[DEC_IRQ_SCC0] = IO_IRQ_NR(KN02CA_IO_INR_SCC0),
@@ -542,10 +537,10 @@
[DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
[DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
[DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
- [DEC_IRQ_SCC0B_RXERR] = IO_IRQ_NR(IO_INR_SCC0B_RXERR),
- [DEC_IRQ_SCC0B_RXDMA] = IO_IRQ_NR(IO_INR_SCC0B_RXDMA),
- [DEC_IRQ_SCC0B_TXERR] = IO_IRQ_NR(IO_INR_SCC0B_TXERR),
- [DEC_IRQ_SCC0B_TXDMA] = IO_IRQ_NR(IO_INR_SCC0B_TXDMA),
+ [DEC_IRQ_AB_RXERR] = IO_IRQ_NR(IO_INR_AB_RXERR),
+ [DEC_IRQ_AB_RXDMA] = IO_IRQ_NR(IO_INR_AB_RXDMA),
+ [DEC_IRQ_AB_TXERR] = IO_IRQ_NR(IO_INR_AB_TXERR),
+ [DEC_IRQ_AB_TXDMA] = IO_IRQ_NR(IO_INR_AB_TXDMA),
[DEC_IRQ_SCC1A_RXERR] = -1,
[DEC_IRQ_SCC1A_RXDMA] = -1,
[DEC_IRQ_SCC1A_TXERR] = -1,
@@ -553,40 +548,35 @@
};
static int_ptr kn02ca_cpu_mask_nr_tbl[][2] __initdata = {
- { { i: DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_MEMORY) },
- { i: DEC_CPU_IRQ_NR(KN02CA_CPU_INR_MEMORY) } },
- { { i: DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_RTC) },
- { i: DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC) } },
- { { i: DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_CASCADE) },
- { p: kn02xa_io_int } },
- { { i: DEC_CPU_IRQ_ALL },
- { p: cpu_all_int } },
+ { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_BUS) },
+ { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS) } },
+ { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_RTC) },
+ { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC) } },
+ { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_CASCADE) },
+ { .p = kn02xa_io_int } },
+ { { .i = DEC_CPU_IRQ_ALL },
+ { .p = cpu_all_int } },
};
static int_ptr kn02ca_asic_mask_nr_tbl[][2] __initdata = {
- { { i: IO_IRQ_DMA },
- { p: asic_dma_int } },
- { { i: IO_IRQ_MASK(KN02CA_IO_INR_SCC0) },
- { i: IO_IRQ_NR(KN02CA_IO_INR_SCC0) } },
- { { i: IO_IRQ_MASK(KN02CA_IO_INR_ASC) },
- { i: IO_IRQ_NR(KN02CA_IO_INR_ASC) } },
- { { i: IO_IRQ_MASK(KN02CA_IO_INR_LANCE) },
- { i: IO_IRQ_NR(KN02CA_IO_INR_LANCE) } },
- { { i: IO_IRQ_MASK(KN02CA_IO_INR_TC1) },
- { i: IO_IRQ_NR(KN02CA_IO_INR_TC1) } },
- { { i: IO_IRQ_MASK(KN02CA_IO_INR_TC0) },
- { i: IO_IRQ_NR(KN02CA_IO_INR_TC0) } },
- { { i: IO_IRQ_ALL },
- { p: asic_all_int } },
+ { { .i = IO_IRQ_DMA },
+ { .p = asic_dma_int } },
+ { { .i = IO_IRQ_MASK(KN02CA_IO_INR_SCC0) },
+ { .i = IO_IRQ_NR(KN02CA_IO_INR_SCC0) } },
+ { { .i = IO_IRQ_MASK(KN02CA_IO_INR_ASC) },
+ { .i = IO_IRQ_NR(KN02CA_IO_INR_ASC) } },
+ { { .i = IO_IRQ_MASK(KN02CA_IO_INR_LANCE) },
+ { .i = IO_IRQ_NR(KN02CA_IO_INR_LANCE) } },
+ { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC1) },
+ { .i = IO_IRQ_NR(KN02CA_IO_INR_TC1) } },
+ { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC0) },
+ { .i = IO_IRQ_NR(KN02CA_IO_INR_TC0) } },
+ { { .i = IO_IRQ_ALL },
+ { .p = asic_all_int } },
};
void __init dec_init_kn02ca(void)
{
- /* Setup some memory addresses. */
- ioasic_base = (void *)KN02CA_IOASIC_BASE;
- dec_rtc_base = (void *)KN02CA_RTC_BASE;
- dec_kn_slot_size = IOASIC_SLOT_SIZE;
-
/* IRQ routing. */
memcpy(&dec_interrupt, &kn02ca_interrupt,
sizeof(kn02ca_interrupt));
@@ -608,7 +598,7 @@
/*
* Machine-specific initialisation for KN03, aka DS5000/240,
* aka 3max+ and DS5900, aka BIGmax. Also applies to KN05, aka
- * DS5000/260, aka 4max+ and DS5900-260.
+ * DS5000/260, aka 4max+ and DS5900/260.
*/
static int kn03_interrupt[DEC_NR_INTS] __initdata = {
[DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN03_CPU_INR_CASCADE),
@@ -621,7 +611,7 @@
[DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN03_CPU_INR_HALT),
[DEC_IRQ_ISDN] = -1,
[DEC_IRQ_LANCE] = IO_IRQ_NR(KN03_IO_INR_LANCE),
- [DEC_IRQ_MEMORY] = DEC_CPU_IRQ_NR(KN03_CPU_INR_MEMORY),
+ [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS),
[DEC_IRQ_PSU] = IO_IRQ_NR(KN03_IO_INR_PSU),
[DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC),
[DEC_IRQ_SCC0] = IO_IRQ_NR(KN03_IO_INR_SCC0),
@@ -644,10 +634,10 @@
[DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
[DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
[DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
- [DEC_IRQ_SCC0B_RXERR] = -1,
- [DEC_IRQ_SCC0B_RXDMA] = -1,
- [DEC_IRQ_SCC0B_TXERR] = -1,
- [DEC_IRQ_SCC0B_TXDMA] = -1,
+ [DEC_IRQ_AB_RXERR] = -1,
+ [DEC_IRQ_AB_RXDMA] = -1,
+ [DEC_IRQ_AB_TXERR] = -1,
+ [DEC_IRQ_AB_TXDMA] = -1,
[DEC_IRQ_SCC1A_RXERR] = IO_IRQ_NR(IO_INR_SCC1A_RXERR),
[DEC_IRQ_SCC1A_RXDMA] = IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
[DEC_IRQ_SCC1A_TXERR] = IO_IRQ_NR(IO_INR_SCC1A_TXERR),
@@ -655,44 +645,39 @@
};
static int_ptr kn03_cpu_mask_nr_tbl[][2] __initdata = {
- { { i: DEC_CPU_IRQ_MASK(KN03_CPU_INR_MEMORY) },
- { i: DEC_CPU_IRQ_NR(KN03_CPU_INR_MEMORY) } },
- { { i: DEC_CPU_IRQ_MASK(KN03_CPU_INR_RTC) },
- { i: DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC) } },
- { { i: DEC_CPU_IRQ_MASK(KN03_CPU_INR_CASCADE) },
- { p: kn03_io_int } },
- { { i: DEC_CPU_IRQ_ALL },
- { p: cpu_all_int } },
+ { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_BUS) },
+ { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS) } },
+ { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_RTC) },
+ { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC) } },
+ { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_CASCADE) },
+ { .p = kn03_io_int } },
+ { { .i = DEC_CPU_IRQ_ALL },
+ { .p = cpu_all_int } },
};
static int_ptr kn03_asic_mask_nr_tbl[][2] __initdata = {
- { { i: IO_IRQ_DMA },
- { p: asic_dma_int } },
- { { i: IO_IRQ_MASK(KN03_IO_INR_SCC0) },
- { i: IO_IRQ_NR(KN03_IO_INR_SCC0) } },
- { { i: IO_IRQ_MASK(KN03_IO_INR_SCC1) },
- { i: IO_IRQ_NR(KN03_IO_INR_SCC1) } },
- { { i: IO_IRQ_MASK(KN03_IO_INR_ASC) },
- { i: IO_IRQ_NR(KN03_IO_INR_ASC) } },
- { { i: IO_IRQ_MASK(KN03_IO_INR_LANCE) },
- { i: IO_IRQ_NR(KN03_IO_INR_LANCE) } },
- { { i: IO_IRQ_MASK(KN03_IO_INR_TC2) },
- { i: IO_IRQ_NR(KN03_IO_INR_TC2) } },
- { { i: IO_IRQ_MASK(KN03_IO_INR_TC1) },
- { i: IO_IRQ_NR(KN03_IO_INR_TC1) } },
- { { i: IO_IRQ_MASK(KN03_IO_INR_TC0) },
- { i: IO_IRQ_NR(KN03_IO_INR_TC0) } },
- { { i: IO_IRQ_ALL },
- { p: asic_all_int } },
+ { { .i = IO_IRQ_DMA },
+ { .p = asic_dma_int } },
+ { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC0) },
+ { .i = IO_IRQ_NR(KN03_IO_INR_SCC0) } },
+ { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC1) },
+ { .i = IO_IRQ_NR(KN03_IO_INR_SCC1) } },
+ { { .i = IO_IRQ_MASK(KN03_IO_INR_ASC) },
+ { .i = IO_IRQ_NR(KN03_IO_INR_ASC) } },
+ { { .i = IO_IRQ_MASK(KN03_IO_INR_LANCE) },
+ { .i = IO_IRQ_NR(KN03_IO_INR_LANCE) } },
+ { { .i = IO_IRQ_MASK(KN03_IO_INR_TC2) },
+ { .i = IO_IRQ_NR(KN03_IO_INR_TC2) } },
+ { { .i = IO_IRQ_MASK(KN03_IO_INR_TC1) },
+ { .i = IO_IRQ_NR(KN03_IO_INR_TC1) } },
+ { { .i = IO_IRQ_MASK(KN03_IO_INR_TC0) },
+ { .i = IO_IRQ_NR(KN03_IO_INR_TC0) } },
+ { { .i = IO_IRQ_ALL },
+ { .p = asic_all_int } },
};
void __init dec_init_kn03(void)
{
- /* Setup some memory addresses. */
- ioasic_base = (void *)KN03_IOASIC_BASE;
- dec_rtc_base = (void *)KN03_RTC_BASE;
- dec_kn_slot_size = IOASIC_SLOT_SIZE;
-
/* IRQ routing. */
memcpy(&dec_interrupt, &kn03_interrupt,
sizeof(kn03_interrupt));
@@ -727,6 +712,7 @@
dec_init_kn02ba();
break;
case MACH_DS5000_2X0: /* DS5000/240 3max+ */
+ case MACH_DS5900: /* DS5900 bigmax */
dec_init_kn03();
break;
case MACH_DS5000_XX: /* Personal DS5000/xx */
@@ -745,7 +731,7 @@
set_except_vector(0, decstation_handle_int);
/* Free the FPU interrupt if the exception is present. */
- if (!(mips_cpu.options & MIPS_CPU_NOFPUEX)) {
+ if (!cpu_has_nofpuex) {
cpu_fpu_mask = 0;
dec_interrupt[DEC_IRQ_FPU] = -1;
}
@@ -756,12 +742,15 @@
if (dec_interrupt[DEC_IRQ_CASCADE] >= 0)
setup_irq(dec_interrupt[DEC_IRQ_CASCADE], &ioirq);
+ /* Register the bus error interrupt. */
+ if (dec_interrupt[DEC_IRQ_BUS] >= 0 && busirq.handler)
+ setup_irq(dec_interrupt[DEC_IRQ_BUS], &busirq);
+
/* Register the HALT interrupt. */
if (dec_interrupt[DEC_IRQ_HALT] >= 0)
setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq);
}
EXPORT_SYMBOL(ioasic_base);
-EXPORT_SYMBOL(dec_rtc_base);
EXPORT_SYMBOL(dec_kn_slot_size);
EXPORT_SYMBOL(dec_interrupt);
FUNET's LINUX-ADM group, linux-adm@nic.funet.fi
TCL-scripts by Sam Shen (who was at: slshen@lbl.gov)