patch-2.3.14 linux/arch/alpha/kernel/core_pyxis.c

• Lines: 190
• Date: Fri Aug 13 11:53:50 1999
• Orig file: v2.3.13/linux/arch/alpha/kernel/core_pyxis.c
• Orig date: Wed Jul 21 15:46:48 1999

diff -u --recursive --new-file v2.3.13/linux/arch/alpha/kernel/core_pyxis.c linux/arch/alpha/kernel/core_pyxis.c
@@ -32,7 +32,6 @@
  */
 
 #define DEBUG_CONFIG 0
-#define DEBUG_MCHECK 0
 
 #if DEBUG_CONFIG
 # define DBG_CNF(args)	printk args
@@ -40,18 +39,6 @@
 # define DBG_CNF(args)
 #endif
 
-#if DEBUG_MCHECK
-# define DBG_MCK(args)	printk args
-# define DEBUG_MCHECK_DUMP
-#else
-# define DBG_MCK(args)
-#endif
-
-
-static volatile unsigned int PYXIS_mcheck_expected = 0;
-static volatile unsigned int PYXIS_mcheck_taken = 0;
-static unsigned int PYXIS_jd;
-
 
 /*
  * Given a bus, device, and function number, compute resulting
@@ -132,8 +119,8 @@
 
 	mb();
 	draina();
-	PYXIS_mcheck_expected = 1;
-	PYXIS_mcheck_taken = 0;
+	mcheck_expected(0) = 1;
+	mcheck_taken(0) = 0;
 	mb();
 
 	/* Access configuration space.  */
@@ -141,12 +128,12 @@
 	mb();
 	mb();  /* magic */
 
-	if (PYXIS_mcheck_taken) {
-		PYXIS_mcheck_taken = 0;
+	if (mcheck_taken(0)) {
+		mcheck_taken(0) = 0;
 		value = 0xffffffffU;
 		mb();
 	}
-	PYXIS_mcheck_expected = 0;
+	mcheck_expected(0) = 0;
 	mb();
 
 	/* If Type1 access, must reset IOC CFG so normal IO space ops work.  */
@@ -186,15 +173,15 @@
 
 	mb();
 	draina();
-	PYXIS_mcheck_expected = 1;
-	PYXIS_mcheck_taken = 0;
+	mcheck_expected(0) = 1;
+	mcheck_taken(0) = 0;
 	mb();
 
 	/* Access configuration space.  */
 	*(vuip)addr = value;
 	mb();
 	temp = *(vuip)addr; /* read back to force the write */
-	PYXIS_mcheck_expected = 0;
+	mcheck_expected(0) = 0;
 	mb();
 
 	/* If Type1 access, must reset IOC CFG so normal IO space ops work.  */
@@ -432,14 +419,13 @@
 	 * Window 1 goes at 3 GB and is 1 GB large.
 	 */
 
-	*(vuip)PYXIS_W0_BASE = PYXIS_DMA_WIN_BASE_DEFAULT | 1UL;
-	*(vuip)PYXIS_W0_MASK = (PYXIS_DMA_WIN_SIZE_DEFAULT - 1) & 0xfff00000U;
-	*(vuip)PYXIS_T0_BASE = 0;
-
-	*(vuip)PYXIS_W1_BASE = (PYXIS_DMA_WIN_BASE_DEFAULT +
-				PYXIS_DMA_WIN_SIZE_DEFAULT) | 1U;
-	*(vuip)PYXIS_W1_MASK = (PYXIS_DMA_WIN_SIZE_DEFAULT - 1) & 0xfff00000U;
-	*(vuip)PYXIS_T1_BASE = PYXIS_DMA_WIN_SIZE_DEFAULT;
+	*(vuip)PYXIS_W0_BASE = PYXIS_DMA_WIN0_BASE_DEFAULT | 1U;
+	*(vuip)PYXIS_W0_MASK = (PYXIS_DMA_WIN0_SIZE_DEFAULT - 1) & 0xfff00000U;
+	*(vuip)PYXIS_T0_BASE = PYXIS_DMA_WIN0_TRAN_DEFAULT >> 2;
+
+	*(vuip)PYXIS_W1_BASE = PYXIS_DMA_WIN1_BASE_DEFAULT | 1U;
+	*(vuip)PYXIS_W1_MASK = (PYXIS_DMA_WIN1_SIZE_DEFAULT - 1) & 0xfff00000U;
+	*(vuip)PYXIS_T1_BASE = PYXIS_DMA_WIN1_TRAN_DEFAULT >> 2;
 
 	*(vuip)PYXIS_W2_BASE = 0x0;
 	*(vuip)PYXIS_W3_BASE = 0x0;
@@ -530,83 +516,26 @@
 	pyxis_finish_init_arch();
 }
 
-static int
+static inline void
 pyxis_pci_clr_err(void)
 {
-	PYXIS_jd = *(vuip)PYXIS_ERR;
-	DBG_MCK(("PYXIS_pci_clr_err: PYXIS ERR after read 0x%x\n", PYXIS_jd));
-	*(vuip)PYXIS_ERR = 0x0180; mb();
-	PYXIS_jd = *(vuip)PYXIS_ERR;  /* re-read to force write */
-	return 0;
+	*(vuip)PYXIS_ERR;
+	*(vuip)PYXIS_ERR = 0x0180;
+	mb();
+	*(vuip)PYXIS_ERR;  /* re-read to force write */
 }
 
 void
 pyxis_machine_check(unsigned long vector, unsigned long la_ptr,
 		    struct pt_regs * regs)
 {
-	struct el_common *mchk_header;
-	struct el_PYXIS_sysdata_mcheck *mchk_sysdata;
-
-	mchk_header = (struct el_common *)la_ptr;
-
-	mchk_sysdata = (struct el_PYXIS_sysdata_mcheck *)
-		(la_ptr + mchk_header->sys_offset);
-
-#if 0
-	DBG_MCK(("pyxis_machine_check: vector=0x%lx la_ptr=0x%lx\n",
-		 vector, la_ptr));
-	DBG_MCK(("\t\t pc=0x%lx size=0x%x procoffset=0x%x sysoffset 0x%x\n",
-		 regs->pc, mchk_header->size, mchk_header->proc_offset,
-		 mchk_header->sys_offset));
-	DBG_MCK(("pyxis_machine_check: expected %d DCSR 0x%lx PEAR 0x%lx\n",
-		 PYXIS_mcheck_expected, mchk_sysdata->epic_dcsr,
-		 mchk_sysdata->epic_pear));
-#endif
-
-	/*
-	 * Check if machine check is due to a badaddr() and if so,
-	 * ignore the machine check.
-	 */
+	/* Clear the error before reporting anything.  */
 	mb();
 	mb();  /* magic */
-	if (PYXIS_mcheck_expected) {
-		DBG_MCK(("PYXIS machine check expected\n"));
-		PYXIS_mcheck_expected = 0;
-		PYXIS_mcheck_taken = 1;
-		mb();
-		mb();  /* magic */
-		draina();
-		pyxis_pci_clr_err();
-		wrmces(0x7);
-		mb();
-	}
-	else {
-		printk("PYXIS machine check NOT expected\n") ;
-		DBG_MCK(("pyxis_machine_check: vector=0x%lx la_ptr=0x%lx\n",
-			 vector, la_ptr));
-		DBG_MCK(("\t\t pc=0x%lx size=0x%x procoffset=0x%x"
-			 " sysoffset 0x%x\n",
-			 regs->pc, mchk_header->size, mchk_header->proc_offset,
-			 mchk_header->sys_offset));
-		PYXIS_mcheck_expected = 0;
-		PYXIS_mcheck_taken = 1;
-		mb();
-		mb();  /* magic */
-		draina();
-		pyxis_pci_clr_err();
-		wrmces(0x7);
-		mb();
+	draina();
+	pyxis_pci_clr_err();
+	wrmces(0x7);
+	mb();
 
-#ifdef DEBUG_MCHECK_DUMP
-		{
-			unsigned long *ptr = (unsigned long *)la_ptr;;
-			long n = mchk_header->size / (2*sizeof(long));
-
-			do
-				printk(" +%lx %lx %lx\n", i*sizeof(long),
-				       ptr[i], ptr[i+1]);
-			while (--i);
-		}
-#endif
-	}
+	process_mcheck_info(vector, la_ptr, regs, "PYXIS", mcheck_expected(0));
 }