patch-2.3.16 linux/arch/arm/kernel/entry-armv.S
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- Lines: 66
- Date:
Mon Aug 30 18:15:11 1999
- Orig file:
v2.3.15/linux/arch/arm/kernel/entry-armv.S
- Orig date:
Mon Aug 2 10:19:52 1999
diff -u --recursive --new-file v2.3.15/linux/arch/arm/kernel/entry-armv.S linux/arch/arm/kernel/entry-armv.S
@@ -16,6 +16,7 @@
#include <asm/errno.h>
#include <asm/hardware.h>
#include <asm/arch/irqs.h>
+#include <asm/proc-fns.h>
#include "../lib/constants.h"
@@ -453,9 +454,13 @@
biceq r0, r0, #I_BIT @ previously
msreq cpsr, r0
mov r0, r2
+#ifdef MULTI_CPU
ldr r2, .LCprocfns
mov lr, pc
- ldr pc, [r2, #4] @ call processor specific code
+ ldr pc, [r2] @ call processor specific code
+#else
+ bl cpu_data_abort
+#endif
mov r3, sp
bl SYMBOL_NAME(do_DataAbort)
ldr r0, [sp, #S_PSR]
@@ -507,7 +512,9 @@
.LCirq: .word __temp_irq
.LCund: .word __temp_und
.LCabt: .word __temp_abt
+#ifdef MULTI_CPU
.LCprocfns: .word SYMBOL_NAME(processor)
+#endif
.LCfp: .word SYMBOL_NAME(fp_enter)
#ifdef CONFIG_ALIGNMENT_TRAP
.LCswi: .word SYMBOL_NAME(cr_alignment)
@@ -540,9 +547,13 @@
mrs r2, cpsr @ Enable interrupts if they were
bic r2, r2, #I_BIT @ previously
msr cpsr, r2
+#ifdef MULTI_CPU
ldr r2, .LCprocfns
mov lr, pc
- ldr pc, [r2, #4] @ call processor specific code
+ ldr pc, [r2] @ call processor specific code
+#else
+ bl cpu_data_abort
+#endif
mov r3, sp
adrsvc al, lr, ret_from_sys_call
b SYMBOL_NAME(do_DataAbort)
@@ -661,7 +672,7 @@
* previous and next are guaranteed not to be the same.
*/
ENTRY(__switch_to)
- stmfd sp!, {r4 - r9, fp, lr} @ Store most regs on stack
+ stmfd sp!, {r4 - sl, fp, lr} @ Store most regs on stack
mrs ip, cpsr
stmfd sp!, {ip} @ Save cpsr_SVC
ldr r2, [r1, #TSS_DOMAIN]
@@ -670,7 +681,7 @@
mcr p15, 0, r2, c3, c0 @ Set domain register
ldmfd sp!, {ip}
msr spsr, ip @ Save tasks CPSR into SPSR for this return
- ldmfd sp!, {r4 - r9, fp, pc}^ @ Load all regs saved previously
+ ldmfd sp!, {r4 - sl, fp, pc}^ @ Load all regs saved previously
.section ".text.init",#alloc,#execinstr
/*
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