patch-2.3.43 linux/drivers/video/aty128fb.c
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- Lines: 2489
- Date:
Tue Feb 8 12:01:59 2000
- Orig file:
v2.3.42/linux/drivers/video/aty128fb.c
- Orig date:
Thu Jan 6 12:57:48 2000
diff -u --recursive --new-file v2.3.42/linux/drivers/video/aty128fb.c linux/drivers/video/aty128fb.c
@@ -1,22 +1,30 @@
-/* $Id: aty128fb.c,v 1.1 1999/10/12 11:00:43 geert Exp $
+/* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $
* linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128
*
- * Copyright (C) Summer 1999, Anthony Tong <atong@uiuc.edu>
+ * Copyright (C) 1999-2000, Anthony Tong <atong@uiuc.edu>
*
- * Brad Douglas <brad@neruo.com>
+ * Brad Douglas <brad@neruo.com>
* - x86 support
* - MTRR
* - Probe ROM for PLL
+ * - modedb
+ *
+ * Ani Joshi / Jeff Garzik
+ * - Code cleanup
*
* Based off of Geert's atyfb.c and vfb.c.
*
* TODO:
* - panning
- * - fix 15/16 bpp on big endian arch's
* - monitor sensing (DDC)
+ * - virtual display
* - other platform support (only ppc/x86 supported)
- * - PPLL_REF_DIV & XTALIN calculation
- * - determine MCLK from previous hardware setting
+ * - PPLL_REF_DIV & XTALIN calculation -done for x86
+ * - determine MCLK from previous setting -done for x86
+ * - calculate XCLK, rather than probe BIOS
+ * - hardware cursor support
+ * - acceleration
+ * - ioctl()'s
*/
/*
@@ -24,6 +32,7 @@
* example code and hardware. Thanks Nitya. -atong
*/
+
#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
@@ -39,7 +48,9 @@
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/selection.h>
+#include <linux/console.h>
#include <linux/pci.h>
+#include <linux/ioport.h>
#include <asm/io.h>
#if defined(CONFIG_PPC)
@@ -49,6 +60,10 @@
#include <video/macmodes.h>
#endif
+#ifdef CONFIG_FB_COMPAT_XPMAC
+#include <asm/vc_ioctl.h>
+#endif
+
#include <video/fbcon.h>
#include <video/fbcon-cfb8.h>
#include <video/fbcon-cfb16.h>
@@ -57,21 +72,30 @@
#ifdef CONFIG_MTRR
#include <asm/mtrr.h>
-#endif
+#endif /* CONFIG_MTRR */
#include "aty128.h"
+/* compatibility with older kernels */
+#ifndef LINUX_VERSION_CODE
+#include <linux/version.h>
+#endif
+
+#ifndef KERNEL_VERSION
+#define KERNEL_VERSION(x,y,z) (((x)<<16)+(y)<<8)+(z))
+#endif
+
+
+/* Debug flag */
#undef DEBUG
-#undef CONFIG_MTRR /* not ready? */
#ifdef DEBUG
-#define DBG(x) printk(KERN_INFO "aty128fb: %s\n",(x));
+#define DBG(x) printk(KERN_DEBUG "aty128fb: %s\n",(x));
#else
#define DBG(x)
#endif
-static char *aty128fb_name = "ATY Rage128";
-
+/* default mode */
static struct fb_var_screeninfo default_var = {
/* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
640, 480, 640, 480, 0, 0, 8, 0,
@@ -80,6 +104,35 @@
0, FB_VMODE_NONINTERLACED
};
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,1)
+#ifndef MODULE
+/* default modedb mode */
+static struct fb_videomode defaultmode __initdata = {
+ /* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */
+ NULL, 60, 640, 480, 39722, 48, 16, 33, 10, 96, 2,
+ 0, FB_VMODE_NONINTERLACED
+};
+#endif
+#endif
+
+/* chip description information */
+struct aty128_chip_info {
+ const char *name;
+ unsigned short vendor;
+ unsigned short device;
+};
+
+/* supported Rage128 chipsets */
+static const struct aty128_chip_info aty128_pci_probe_list[] =
+{
+ {"PCI_DEVICE_ID_ATI_RAGE128_RE", PCI_VENDOR_ID_ATI, 0x5245},
+ {"PCI_DEVICE_ID_ATI_RAGE128_RF", PCI_VENDOR_ID_ATI, 0x5246},
+ {"PCI_DEVICE_ID_ATI_RAGE128_RK", PCI_VENDOR_ID_ATI, 0x524b},
+ {"PCI_DEVICE_ID_ATI_RAGE128_RL", PCI_VENDOR_ID_ATI, 0x524c},
+ {NULL, 0, 0}
+};
+
+/* packed BIOS settings */
#pragma pack(1)
typedef struct {
u8 clock_chip_type;
@@ -107,6 +160,7 @@
} PLL_BLOCK;
#pragma pack()
+/* onboard memory information */
struct aty128_meminfo {
u8 ML;
u8 MB;
@@ -120,23 +174,32 @@
u8 Rloop;
};
+/* various memory configurations */
const struct aty128_meminfo sdr_128 = { 4, 4, 3, 3, 1, 3, 1, 16, 30, 16 };
const struct aty128_meminfo sdr_64 = { 4, 8, 3, 3, 1, 3, 1, 17, 46, 17 };
const struct aty128_meminfo sdr_sgram = { 4, 4, 1, 2, 1, 2, 1, 16, 24, 16 };
const struct aty128_meminfo ddr_sgram = { 4, 4, 3, 3, 2, 3, 1, 16, 31, 16 };
static int currcon = 0;
+
+static char *aty128fb_name = "ATY Rage128";
static char fontname[40] __initdata = { 0 };
+static char noaccel __initdata = 0;
+
+#ifndef MODULE
+static const char *mode_option __initdata = NULL;
+#endif
#if defined(CONFIG_PPC)
-static int default_vmode __initdata = VMODE_NVRAM;
-static int default_cmode __initdata = CMODE_NVRAM;
+static int default_vmode __initdata = VMODE_CHOOSE;
+static int default_cmode __initdata = CMODE_8;
#endif
-#if defined(CONFIG_MTRR)
+#ifdef CONFIG_MTRR
static int mtrr = 1;
-#endif
+#endif /* CONFIG_MTRR */
+/* PLL constants */
struct aty128_constants {
u32 dotclock;
u32 ppll_min;
@@ -154,6 +217,7 @@
u32 v_total, v_sync_strt_wid;
u32 pitch;
u32 offset, offset_cntl;
+ u32 xoffset, yoffset;
u32 vxres, vyres;
u32 bpp;
};
@@ -179,17 +243,19 @@
struct fb_info_aty128 {
struct fb_info fb_info;
+ struct fb_info_aty128 *next;
struct aty128_constants constants;
- unsigned long regbase_phys, regbase;
- unsigned long frame_buffer_phys, frame_buffer;
- const struct aty128_meminfo *mem;
- u32 vram_size;
- u32 BIOS_SEG;
-#ifdef CONFIG_MTRR
- struct { int vram; int vram_valid; } mtrr;
-#endif
+ unsigned long regbase_phys; /* mmio */
+ unsigned long frame_buffer_phys; /* framebuffer memory */
+ unsigned long frame_buffer; /* remaped framebuffer */
+ void *regbase;
+ const struct aty128_meminfo *mem; /* onboard mem info */
+ u32 vram_size; /* onboard video ram */
+ void *BIOS_SEG; /* BIOS segment */
+ unsigned short card_revision; /* video card revision */
struct aty128fb_par default_par, current_par;
struct display disp;
+ struct display_switch dispsw; /* for cursor and font */
struct { u8 red, green, blue, pad; } palette[256];
union {
#ifdef FBCON_HAS_CFB16
@@ -203,8 +269,16 @@
#endif
} fbcon_cmap;
int blitter_may_be_busy;
+#ifdef CONFIG_PCI
+ struct pci_dev *pdev;
+#endif
+#ifdef CONFIG_MTRR
+ struct { int vram; int vram_valid; } mtrr;
+#endif /* CONFIG_MTRR */
};
+static struct fb_info_aty128 *board_list = NULL;
+
#define round_div(n, d) ((n+(d/2))/d)
/*
@@ -226,7 +300,7 @@
static int aty128fb_set_cmap(struct fb_cmap *cmap, int kspc, int con,
struct fb_info *info);
static int aty128fb_pan_display(struct fb_var_screeninfo *var, int con,
- struct fb_info *info);
+ struct fb_info *fb);
static int aty128fb_ioctl(struct inode *inode, struct file *file, u_int cmd,
u_long arg, int con, struct fb_info *info);
@@ -242,7 +316,6 @@
static int aty128fbcon_switch(int con, struct fb_info *info);
static void aty128fbcon_blank(int blank, struct fb_info *info);
-
/*
* Internal routines
*/
@@ -257,20 +330,43 @@
static int aty128_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info);
static void do_install_cmap(int con, struct fb_info *info);
+#ifndef CONFIG_FB_OF
static void aty128pci_probe(void);
+static int aty128_pci_register(struct pci_dev *pdev,
+ const struct aty128_chip_info *aci);
+#endif
+static struct fb_info_aty128 *aty128_board_list_add(struct fb_info_aty128
+ *board_list, struct fb_info_aty128 *new_node);
+#ifndef CONFIG_PPC
static int aty128find_ROM(struct fb_info_aty128 *info);
-static void aty128_timings(struct fb_info_aty128 *info);
static void aty128_get_pllinfo(struct fb_info_aty128 *info);
+#endif
+static void aty128_timings(struct fb_info_aty128 *info);
+static void aty128_init_engine(const struct aty128fb_par *par,
+ struct fb_info_aty128 *info);
static void aty128_reset_engine(const struct fb_info_aty128 *info);
static void aty128_flush_pixel_cache(const struct fb_info_aty128 *info);
static void wait_for_fifo(u16 entries, const struct fb_info_aty128 *info);
-static void wait_for_idle(const struct fb_info_aty128 *info);
+static void wait_for_idle(struct fb_info_aty128 *info);
static u32 bpp_to_depth(u32 bpp);
#ifdef FBCON_HAS_CFB8
static struct display_switch fbcon_aty128_8;
+static void fbcon_aty8_putc(struct vc_data *conp, struct display *p,
+ int c, int yy, int xx);
+static void fbcon_aty8_putcs(struct vc_data *conp, struct display *p,
+ const unsigned short *s, int count,
+ int yy, int xx);
+#endif
+#ifdef FBCON_HAS_CFB16
+static struct display_switch fbcon_aty128_16;
+#endif
+#ifdef FBCON_HAS_CFB24
+static struct display_switch fbcon_aty128_24;
+#endif
+#ifdef FBCON_HAS_CFB32
+static struct display_switch fbcon_aty128_32;
#endif
-
static struct fb_ops aty128fb_ops = {
aty128fb_open, aty128fb_release, aty128fb_get_fix,
@@ -285,64 +381,58 @@
* or using the other register aperture? TODO.
*/
static inline u32
-_aty_ld_le32(volatile unsigned int regindex,
+_aty_ld_le32(volatile unsigned int regindex,
const struct fb_info_aty128 *info)
{
- unsigned long temp;
+ unsigned long *temp;
u32 val;
#if defined(__powerpc__)
eieio();
temp = info->regbase;
asm("lwbrx %0,%1,%2" : "=b"(val) : "b" (regindex), "b" (temp));
-#elif defined(__sparc_v9__)
- temp = info->regbase + regindex;
- asm("lduwa [%1] %2, %0" : "=r" (val) : "r" (temp), "i" (ASI_PL));
#else
temp = info->regbase+regindex;
- val = le32_to_cpu(*((volatile u32 *)(temp)));
+ val = readl (temp);
#endif
+
return val;
}
static inline void
-_aty_st_le32(volatile unsigned int regindex, u32 val,
+_aty_st_le32(volatile unsigned int regindex, u32 val,
const struct fb_info_aty128 *info)
{
- unsigned long temp;
+ unsigned long *temp;
#if defined(__powerpc__)
- eieio();
temp = info->regbase;
- asm("stwbrx %0,%1,%2" : : "b" (val), "b" (regindex), "b" (temp) :
+ asm("stwbrx %0,%1,%2" : : "r" (val), "b" (regindex), "r" (temp) :
"memory");
-#elif defined(__sparc_v9__)
- temp = info->regbase + regindex;
- asm("stwa %0, [%1] %2" : : "r" (val), "r" (temp), "i" (ASI_PL) : "memory");
+#elif defined(__mc68000__)
+ *((volatile u32 *)(info->regbase+regindex)) = cpu_to_le32(val);
#else
temp = info->regbase+regindex;
- *((volatile u32 *)(temp)) = cpu_to_le32(val);
+ writel (val, temp);
#endif
}
static inline u8
-_aty_ld_8(volatile unsigned int regindex,
- const struct fb_info_aty128 *info)
+_aty_ld_8(unsigned int regindex, const struct fb_info_aty128 *info)
{
#if defined(__powerpc__)
eieio();
#endif
- return *(volatile u8 *)(info->regbase+regindex);
+ return readb (info->regbase + regindex);
}
static inline void
-_aty_st_8(volatile unsigned int regindex, u8 val,
- const struct fb_info_aty128 *info)
+_aty_st_8(unsigned int regindex, u8 val, const struct fb_info_aty128 *info)
{
#if defined(__powerpc__)
eieio();
#endif
- *(volatile u8 *)(info->regbase+regindex) = val;
+ writeb (val, info->regbase + regindex);
}
#define aty_ld_le32(regindex) _aty_ld_le32(regindex, info)
@@ -357,18 +447,26 @@
#define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, info)
#define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, info)
+
static u32
_aty_ld_pll(unsigned int pll_index,
const struct fb_info_aty128 *info)
{
+#if defined(__powerpc__)
+ eieio();
+#endif
aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x1F);
return aty_ld_le32(CLOCK_CNTL_DATA);
}
+
static void
_aty_st_pll(unsigned int pll_index, u32 val,
const struct fb_info_aty128 *info)
-{
+{
+#if defined(__powerpc__)
+ eieio();
+#endif
aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x1F) | PLL_WR_EN);
aty_st_le32(CLOCK_CNTL_DATA, val);
}
@@ -380,6 +478,7 @@
return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R);
}
+
static void
aty_pll_wait_readupdate(const struct fb_info_aty128 *info)
{
@@ -394,10 +493,11 @@
#ifdef DEBUG
if (reset) /* reset engine?? */
- printk(KERN_ERR "aty128fb: PLL write timeout!");
+ DBG("PLL write timeout!");
#endif
}
+
/* tell PLL to update */
static void
aty_pll_writeupdate(const struct fb_info_aty128 *info)
@@ -431,10 +531,10 @@
/*
- * Accelerator functions
+ * Accelerator engine functions
*/
static void
-wait_for_idle(const struct fb_info_aty128 *info)
+wait_for_idle(struct fb_info_aty128 *info)
{
unsigned long timeout = jiffies + HZ/20;
int reset = 1;
@@ -449,6 +549,8 @@
if (reset)
aty128_reset_engine(info);
+
+ info->blitter_may_be_busy = 0;
}
@@ -476,7 +578,7 @@
aty_st_le32(PC_NGUI_CTLSTAT, aty_ld_le32(PC_NGUI_CTLSTAT) | 0x000000ff);
- while (i && (aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY))
+ while (i && ((aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY) == PC_BUSY))
i--;
}
@@ -507,31 +609,33 @@
aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4);
#ifdef DEBUG
- printk("aty128fb: engine reset\n");
+ DBG("engine reset");
#endif
}
static void
aty128_init_engine(const struct aty128fb_par *par,
- const struct fb_info_aty128 *info)
+ struct fb_info_aty128 *info)
{
- u32 temp;
+ u32 pitch_value;
+
+ /* 3D scaler not spoken here */
aty_st_le32(SCALE_3D_CNTL, 0x00000000);
aty128_reset_engine(info);
- temp = par->crtc.pitch; /* fix this up */
+ pitch_value = par->crtc.pitch; /* fix this up */
if (par->crtc.bpp == 24) {
- temp = temp * 3;
+ pitch_value = pitch_value * 3;
}
/* setup engine offset registers */
- wait_for_fifo(4, info);
+ wait_for_fifo(1, info);
aty_st_le32(DEFAULT_OFFSET, 0x00000000);
/* setup engine pitch registers */
- aty_st_le32(DEFAULT_PITCH, temp);
+ aty_st_le32(DEFAULT_PITCH, pitch_value);
/* set the default scissor register to max dimensions */
wait_for_fifo(1, info);
@@ -540,21 +644,22 @@
/* set the drawing controls registers */
wait_for_fifo(1, info);
aty_st_le32(DP_GUI_MASTER_CNTL,
- GMC_SRC_PITCH_OFFSET_DEFAULT |
- GMC_DST_PITCH_OFFSET_DEFAULT |
- GMC_SRC_CLIP_DEFAULT |
- GMC_DST_CLIP_DEFAULT |
- GMC_BRUSH_SOLIDCOLOR |
- (bpp_to_depth(par->crtc.bpp) << 8) |
- GMC_SRC_DSTCOLOR |
- GMC_BYTE_ORDER_MSB_TO_LSB |
- GMC_DP_CONVERSION_TEMP_6500 |
- ROP3_PATCOPY |
- GMC_DP_SRC_RECT |
- GMC_3D_FCN_EN_CLR |
- GMC_DST_CLR_CMP_FCN_CLEAR |
- GMC_AUX_CLIP_CLEAR |
- GMC_WRITE_MASK_SET);
+ GMC_SRC_PITCH_OFFSET_DEFAULT |
+ GMC_DST_PITCH_OFFSET_DEFAULT |
+ GMC_SRC_CLIP_DEFAULT |
+ GMC_DST_CLIP_DEFAULT |
+ GMC_BRUSH_SOLIDCOLOR |
+ (bpp_to_depth(par->crtc.bpp) << 8) |
+ GMC_SRC_DSTCOLOR |
+ GMC_BYTE_ORDER_MSB_TO_LSB |
+ GMC_DP_CONVERSION_TEMP_6500 |
+ ROP3_PATCOPY |
+ GMC_DP_SRC_RECT |
+ GMC_3D_FCN_EN_CLR |
+ GMC_DST_CLR_CMP_FCN_CLEAR |
+ GMC_AUX_CLIP_CLEAR |
+ GMC_WRITE_MASK_SET);
+
wait_for_fifo(8, info);
/* clear the line drawing registers */
@@ -563,12 +668,12 @@
aty_st_le32(DST_BRES_DEC, 0);
/* set brush color registers */
- aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF);
- aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000);
+ aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */
+ aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */
/* set source color registers */
- aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF);
- aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000);
+ aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */
+ aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */
/* default write mask */
aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF);
@@ -578,39 +683,33 @@
}
- /*
- * CRTC programming
- */
-
/* convert bpp values to their register representation */
static u32
bpp_to_depth(u32 bpp)
{
if (bpp <= 8)
- return 2;
- else if (bpp <= 15)
- return 3;
+ return DST_8BPP;
else if (bpp <= 16)
-#if 0 /* force 15bpp */
- return 4;
-#else
- return 3;
-#endif
+ return DST_15BPP;
else if (bpp <= 24)
- return 5;
+ return DST_24BPP;
else if (bpp <= 32)
- return 6;
+ return DST_32BPP;
return -EINVAL;
}
+ /*
+ * CRTC programming
+ */
+
+/* Program the CRTC registers */
static void
aty128_set_crtc(const struct aty128_crtc *crtc,
const struct fb_info_aty128 *info)
{
aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl);
- // aty_st_le32(CRTC_EXT_CNTL, crtc->ext_cntl);
aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total);
aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid);
aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total);
@@ -630,8 +729,9 @@
u32 left, right, upper, lower, hslen, vslen, sync, vmode;
u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol;
u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
- u32 depth;
+ u32 depth, bytpp;
u8 hsync_strt_pix[5] = { 0, 0x12, 9, 6, 5 };
+ u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 };
/* input */
xres = var->xres;
@@ -666,60 +766,74 @@
if (vyres < yres + yoffset)
vyres = yres + yoffset;
- if (bpp <= 8)
- bpp = 8;
- else if (bpp <= 16)
- bpp = 16;
- else if (bpp <= 32)
- bpp = 32;
+ depth = bpp_to_depth(bpp);
- if (vxres * vyres * (bpp/8) > info->vram_size)
- return -EINVAL;
+ /* make sure we didn't get an invalid depth */
+ if (depth == -EINVAL) {
+ printk(KERN_ERR "aty128fb: Invalid depth\n");
+ return -EINVAL;
+ }
- h_disp = xres / 8 - 1;
- h_total = (xres + right + hslen + left) / 8 - 1;
+ bytpp = mode_bytpp[depth];
+
+ /* make sure there is enough video ram for the mode */
+ if ((u32)(vxres * vyres * bytpp) > info->vram_size) {
+ printk(KERN_ERR "aty128fb: Not enough memory for mode\n");
+ return -EINVAL;
+ }
+
+ h_disp = (xres/8) - 1;
+ h_total = (((xres + right + hslen + left) / 8) - 1) & 0xFFFFL;
v_disp = yres - 1;
- v_total = yres + upper + vslen + lower - 1;
+ v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL;
+
+ /* check to make sure h_total and v_total are in range */
+ if ((h_total/8 - 1) > 0x1ff || (v_total - 1) > 0x7FF) {
+ printk(KERN_ERR "aty128fb: invalid width ranges\n");
+ return -EINVAL;
+ }
- h_sync_wid = hslen / 8;
+ h_sync_wid = (hslen+7)/8;
if (h_sync_wid == 0)
h_sync_wid = 1;
- else if (h_sync_wid > 0x3f)
+ else if (h_sync_wid > 0x3f) /* 0x3f = max hwidth */
h_sync_wid = 0x3f;
- h_sync_strt = (xres + right - 8) + hsync_strt_pix[bpp/8];
+ h_sync_strt = h_disp + (right/8);
- v_disp = yres - 1;
v_sync_wid = vslen;
if (v_sync_wid == 0)
v_sync_wid = 1;
- else if (v_sync_wid > 0x1f)
+ else if (v_sync_wid > 0x1f) /* 0x1f = max vwidth */
v_sync_wid = 0x1f;
- v_sync_strt = yres + lower - 1;
+ v_sync_strt = v_disp + lower;
- h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : (1 << 23);
- v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : (1 << 23);
-
- depth = bpp_to_depth(bpp);
+ h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
+ v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
+
c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
- crtc->gen_cntl = 0x03000000 | c_sync | depth << 8;
+ crtc->gen_cntl = 0x03000000L | c_sync | (depth << 8);
- crtc->h_total = (h_disp << 16) | (h_total & 0x0000FFFF);
- crtc->v_total = (v_disp << 16) | (v_total & 0x0000FFFF);
+ crtc->h_total = h_total | (h_disp << 16);
+ crtc->v_total = v_total | (v_disp << 16);
- crtc->h_sync_strt_wid = (h_sync_wid << 16) | (h_sync_strt) | h_sync_pol;
- crtc->v_sync_strt_wid = (v_sync_wid << 16) | (v_sync_strt) | v_sync_pol;
+ crtc->h_sync_strt_wid = hsync_strt_pix[bytpp] | (h_sync_strt << 3) |
+ (h_sync_wid << 16) | (h_sync_pol << 23);
+ crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) |
+ (v_sync_pol << 23);
- crtc->pitch = xres / 8;
+ crtc->pitch = xres >> 3;
crtc->offset = 0;
crtc->offset_cntl = 0;
crtc->vxres = vxres;
crtc->vyres = vyres;
+ crtc->xoffset = xoffset;
+ crtc->yoffset = yoffset;
crtc->bpp = bpp;
return 0;
@@ -727,27 +841,85 @@
static int
+aty128_bpp_to_var(int pix_width, struct fb_var_screeninfo *var)
+{
+
+ /* fill in pixel info */
+ switch (pix_width) {
+ case CRTC_PIX_WIDTH_8BPP:
+ var->bits_per_pixel = 8;
+ var->red.offset = 0;
+ var->red.length = 8;
+ var->green.offset = 0;
+ var->green.length = 8;
+ var->blue.offset = 0;
+ var->blue.length = 8;
+ var->transp.offset = 0;
+ var->transp.length = 0;
+ break;
+ case CRTC_PIX_WIDTH_15BPP:
+ case CRTC_PIX_WIDTH_16BPP:
+ var->bits_per_pixel = 16;
+ var->red.offset = 10;
+ var->red.length = 5;
+ var->green.offset = 5;
+ var->green.length = 5;
+ var->blue.offset = 0;
+ var->blue.length = 5;
+ var->transp.offset = 0;
+ var->transp.length = 0;
+ break;
+ case CRTC_PIX_WIDTH_24BPP:
+ var->bits_per_pixel = 24;
+ var->red.offset = 16;
+ var->red.length = 8;
+ var->green.offset = 8;
+ var->green.length = 8;
+ var->blue.offset = 0;
+ var->blue.length = 8;
+ var->transp.offset = 0;
+ var->transp.length = 0;
+ break;
+ case CRTC_PIX_WIDTH_32BPP:
+ var->bits_per_pixel = 32;
+ var->red.offset = 16;
+ var->red.length = 8;
+ var->green.offset = 8;
+ var->green.length = 8;
+ var->blue.offset = 0;
+ var->blue.length = 8;
+ var->transp.offset = 24;
+ var->transp.length = 8;
+ break;
+ default:
+ printk(KERN_ERR "Invalid pixel width\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+
+static int
aty128_crtc_to_var(const struct aty128_crtc *crtc,
struct fb_var_screeninfo *var)
{
-#ifdef notyet /* xoffset and yoffset are not correctly calculated */
- u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
+ u32 xres, yres, left, right, upper, lower, hslen, vslen, sync;
u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
u32 pix_width;
h_total = crtc->h_total & 0x1ff;
h_disp = (crtc->h_total>>16) & 0xff;
- h_sync_strt = (crtc->h_sync_strt_wid & 0xff) |
- ((crtc->h_sync_strt_wid>>4) & 0x100);
- h_sync_dly = (crtc->h_sync_strt_wid>>8) & 0x7;
- h_sync_wid = (crtc->h_sync_strt_wid>>16) & 0x1f;
- h_sync_pol = (crtc->h_sync_strt_wid>>21) & 0x1;
+ h_sync_strt = (crtc->h_sync_strt_wid>>3) & 0x1ff;
+ h_sync_dly = crtc->h_sync_strt_wid & 0x7;
+ h_sync_wid = (crtc->h_sync_strt_wid>>16) & 0x3f;
+ h_sync_pol = (crtc->h_sync_strt_wid>>23) & 0x1;
v_total = crtc->v_total & 0x7ff;
v_disp = (crtc->v_total>>16) & 0x7ff;
v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
v_sync_wid = (crtc->v_sync_strt_wid>>16) & 0x1f;
- v_sync_pol = (crtc->v_sync_strt_wid>>21) & 0x1;
+ v_sync_pol = (crtc->v_sync_strt_wid>>23) & 0x1;
c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
@@ -760,88 +932,15 @@
lower = v_sync_strt-v_disp;
vslen = v_sync_wid;
sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
- (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
- (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
+ (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
+ (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
- switch (pix_width) {
-#if 0
- case CRTC_PIX_WIDTH_4BPP:
- bpp = 4;
- var->red.offset = 0;
- var->red.length = 8;
- var->green.offset = 0;
- var->green.length = 8;
- var->blue.offset = 0;
- var->blue.length = 8;
- var->transp.offset = 0;
- var->transp.length = 0;
- break;
-#endif
- case CRTC_PIX_WIDTH_8BPP:
- bpp = 8;
- var->red.offset = 0;
- var->red.length = 8;
- var->green.offset = 0;
- var->green.length = 8;
- var->blue.offset = 0;
- var->blue.length = 8;
- var->transp.offset = 0;
- var->transp.length = 0;
- break;
- case CRTC_PIX_WIDTH_15BPP:
- bpp = 16;
- var->red.offset = 10;
- var->red.length = 5;
- var->green.offset = 5;
- var->green.length = 5;
- var->blue.offset = 0;
- var->blue.length = 5;
- var->transp.offset = 0;
- var->transp.length = 0;
- break;
- case CRTC_PIX_WIDTH_16BPP:
- bpp = 16;
- var->red.offset = 11;
- var->red.length = 5;
- var->green.offset = 5;
- var->green.length = 6;
- var->blue.offset = 0;
- var->blue.length = 5;
- var->transp.offset = 0;
- var->transp.length = 0;
- break;
- case CRTC_PIX_WIDTH_24BPP:
- bpp = 24;
- var->red.offset = 16;
- var->red.length = 8;
- var->green.offset = 8;
- var->green.length = 8;
- var->blue.offset = 0;
- var->blue.length = 8;
- var->transp.offset = 0;
- var->transp.length = 0;
- break;
- case CRTC_PIX_WIDTH_32BPP:
- bpp = 32;
- var->red.offset = 16;
- var->red.length = 8;
- var->green.offset = 8;
- var->green.length = 8;
- var->blue.offset = 0;
- var->blue.length = 8;
- var->transp.offset = 24;
- var->transp.length = 8;
- break;
- default:
- printk(KERN_ERR "Invalid pixel width\n");
- }
+ aty128_bpp_to_var(pix_width, var);
-//Godda do math for xoffset and yoffset: does not exist in crtc
var->xres = xres;
var->yres = yres;
var->xres_virtual = crtc->vxres;
var->yres_virtual = crtc->vyres;
- var->bits_per_pixel = bpp;
var->xoffset = crtc->xoffset;
var->yoffset = crtc->yoffset;
var->left_margin = left;
@@ -853,59 +952,6 @@
var->sync = sync;
var->vmode = FB_VMODE_NONINTERLACED;
-#endif /* notyet */
- return 0;
-}
-
-static int
-aty128_bpp_to_var(int bpp, struct fb_var_screeninfo *var)
-{
- /* fill in pixel info */
- switch (bpp) {
- case 8:
- var->red.offset = 0;
- var->red.length = 8;
- var->green.offset = 0;
- var->green.length = 8;
- var->blue.offset = 0;
- var->blue.length = 8;
- var->transp.offset = 0;
- var->transp.length = 0;
- break;
- case 15:
- var->bits_per_pixel = 16;
- var->red.offset = 10;
- var->red.length = 5;
- var->green.offset = 5;
- var->green.length = 5;
- var->blue.offset = 0;
- var->blue.length = 5;
- var->transp.offset = 15;
- var->transp.length = 1;
- break;
- case 16:
- var->bits_per_pixel = 16;
- var->red.offset = 11;
- var->red.length = 5;
- var->green.offset = 5;
- var->green.length = 6;
- var->blue.offset = 0;
- var->blue.length = 5;
- var->transp.offset = 0;
- var->transp.length = 0;
- break;
- case 32:
- var->red.offset = 16;
- var->red.length = 8;
- var->green.offset = 8;
- var->green.length = 8;
- var->blue.offset = 0;
- var->blue.length = 8;
- var->transp.offset = 24;
- var->transp.length = 8;
- break;
- }
-
return 0;
}
@@ -914,16 +960,22 @@
aty128_set_pll(struct aty128_pll *pll, const struct fb_info_aty128 *info)
{
int div3;
+
unsigned char post_conv[] = /* register values for post dividers */
- { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 };
+ { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 };
/* select PPLL_DIV_3 */
aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8));
- /* reset ppll */
+ /* reset PLL */
aty_st_pll(PPLL_CNTL,
aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN);
+ /* write the reference divider */
+ aty_st_pll(PPLL_REF_DIV, info->constants.ref_divider & 0x3ff);
+ aty_pll_writeupdate(info);
+ aty_pll_wait_readupdate(info);
+
div3 = aty_ld_pll(PPLL_DIV_3);
div3 &= ~PPLL_FB3_DIV_MASK;
@@ -947,22 +999,23 @@
static int
-aty128_var_to_pll(u32 vclk_per, struct aty128_pll *pll,
+aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll,
const struct fb_info_aty128 *info)
{
const struct aty128_constants c = info->constants;
unsigned char post_dividers [] = {1,2,4,8,3,6,12};
- u32 output_freq, vclk;
+ u32 output_freq;
+ u32 vclk; /* in .01 MHz */
int i;
u32 n, d;
- vclk = 100000000 / vclk_per; /* convert units to 10 kHz */
+ vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */
/* adjust pixel clock if necessary */
if (vclk > c.ppll_max)
vclk = c.ppll_max;
if (vclk * 12 < c.ppll_min)
- vclk = c.ppll_min;
+ vclk = c.ppll_min/12;
/* now, find an acceptable divider */
for (i = 0; i < sizeof(post_dividers); i++) {
@@ -970,17 +1023,20 @@
if (output_freq >= c.ppll_min && output_freq <= c.ppll_max)
break;
}
- pll->post_divider = post_dividers[i];
/* calculate feedback divider */
n = c.ref_divider * output_freq;
d = c.dotclock;
- pll->feedback_divider = round_div(n, d);
+ pll->post_divider = post_dividers[i];
+ pll->feedback_divider = round_div(n, d);
pll->vclk = vclk;
+
#ifdef DEBUG
- printk("post %x feedback %x vlck %x output %x\n",
- pll->post_divider, pll->feedback_divider, vclk, output_freq);
+ printk(KERN_DEBUG "var_to_pll: post %d feedback %d vlck %d output %d ref_divider %d\n",
+ pll->post_divider, pll->feedback_divider, vclk, output_freq,
+ c.ref_divider);
+ printk(KERN_DEBUG "var_to_pll: vclk_per: %d\n", period_in_ps);
#endif
return 0;
@@ -988,9 +1044,11 @@
static int
-aty128_pll_to_var(const struct aty128_pll *pll, struct fb_var_screeninfo *var)
+aty128_pll_to_var(const struct aty128_pll *pll, struct fb_var_screeninfo *var,
+ const struct fb_info_aty128 *info)
{
- /* TODO */
+ var->pixclock = 100000000 / pll->vclk;
+
return 0;
}
@@ -1017,6 +1075,7 @@
s32 x, b, p, ron, roff;
u32 n, d;
+ /* 15bpp is really 16bpp */
if (bpp == 15)
bpp = 16;
@@ -1033,7 +1092,7 @@
x;
#ifdef DEBUG
- printk("x %x\n", x);
+ printk(KERN_DEBUG "x %x\n", x);
#endif
b = 0;
while (x) {
@@ -1048,13 +1107,13 @@
x = round_div(n, d);
roff = x * (fifo_depth - 4);
if ((ron + m->Rloop) >= roff) {
- printk("Mode out of range\n");
+ printk(KERN_ERR "Mode out of range\n");
return -EINVAL;
}
#ifdef DEBUG
- printk("p: %x rloop: %x x: %x ron: %x roff: %x\n", p, m->Rloop, x,
- ron, roff);
+ printk(KERN_DEBUG "p: %x rloop: %x x: %x ron: %x roff: %x\n", p,
+ m->Rloop, x, ron, roff);
#endif
dsp->dda_config = p << 16 | m->Rloop << 20 | x;
dsp->dda_on_off = ron << 16 | roff;
@@ -1073,6 +1132,9 @@
u32 config;
info->current_par = *par;
+
+ if (info->blitter_may_be_busy)
+ wait_for_idle(info);
/* clear all registers that may interfere with mode setting */
aty_st_le32(OVR_CLR, 0);
@@ -1083,7 +1145,7 @@
aty_st_le32(MPP_GP_CONFIG, 0);
aty_st_le32(SUBPIC_CNTL, 0);
aty_st_le32(VIPH_CONTROL, 0);
- aty_st_le32(I2C_CNTL_1, 0);
+ aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */
aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */
aty_st_le32(CAP0_TRIG_CNTL, 0);
aty_st_le32(CAP1_TRIG_CNTL, 0);
@@ -1104,8 +1166,10 @@
#endif
aty_st_le32(CONFIG_CNTL, config);
-
aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */
+
+ if (par->accel_flags & FB_ACCELF_TEXT)
+ aty128_init_engine(par, info);
}
@@ -1127,6 +1191,10 @@
}
+ /*
+ * encode/decode the User Defined Part of the Display
+ */
+
static int
aty128_decode_var(struct fb_var_screeninfo *var, struct aty128fb_par *par,
const struct fb_info_aty128 *info)
@@ -1158,17 +1226,19 @@
{
int err;
- //memset(var, 0, sizeof(struct fb_var_screeninfo));
-
- /* XXX aty128_*_to_var() aren't fully implemented! */
if ((err = aty128_crtc_to_var(&par->crtc, var)))
return err;
- if ((err = aty128_pll_to_var(&par->pll, var)))
+ if ((err = aty128_pll_to_var(&par->pll, var, info)))
return err;
- if ((err = aty128_bpp_to_var(var->bits_per_pixel, var)))
- return err;
+ var->red.msb_right = 0;
+ var->green.msb_right = 0;
+ var->blue.msb_right = 0;
+ var->transp.msb_right = 0;
+
+ var->nonstd = 0;
+ var->activate = 0;
var->height = -1;
var->width = -1;
@@ -1210,6 +1280,26 @@
display = (con >= 0) ? &fb_display[con] : fb->disp;
+ /* basic (in)sanity checks */
+ if (!var->xres)
+ var->xres = 1;
+ if (!var->yres)
+ var->yres = 1;
+ if (var->xres > var->xres_virtual)
+ var->xres_virtual = var->xres;
+ if (var->yres > var->yres_virtual)
+ var->yres_virtual = var->yres;
+ if (var->bits_per_pixel <= 8)
+ var->bits_per_pixel = 8;
+ else if (var->bits_per_pixel <= 16)
+ var->bits_per_pixel = 16;
+ else if (var->bits_per_pixel <= 24)
+ var->bits_per_pixel = 24;
+ else if (var->bits_per_pixel <= 32)
+ var->bits_per_pixel = 32;
+ else
+ return -EINVAL;
+
if ((err = aty128_decode_var(var, &par, info)))
return err;
@@ -1230,8 +1320,9 @@
oldbpp != var->bits_per_pixel || oldaccel != var->accel_flags) {
struct fb_fix_screeninfo fix;
+
aty128_encode_fix(&fix, &par, info);
- display->screen_base = (char *) info->frame_buffer;
+ display->screen_base = (char *)info->frame_buffer;
display->visual = fix.visual;
display->type = fix.type;
display->type_aux = fix.type_aux;
@@ -1242,13 +1333,11 @@
display->inverse = 0;
accel = var->accel_flags & FB_ACCELF_TEXT;
- aty128_set_disp(display, info, var->bits_per_pixel, accel);
+ aty128_set_disp(display, info, par.crtc.bpp, accel);
-#if 0 /* acceleration is not ready */
if (accel)
- display->scrollmode = 0;
+ display->scrollmode = SCROLL_YNOMOVE;
else
-#endif
display->scrollmode = SCROLL_YREDRAW;
if (info->fb_info.changevar)
@@ -1264,6 +1353,26 @@
do_install_cmap(con, &info->fb_info);
}
+#ifdef CONFIG_FB_COMPAT_XPMAC
+ if (console_fb_info == &info->fb_info) {
+ int vmode, cmode;
+
+ display_info.width = var->xres;
+ display_info.height = var->yres;
+ display_info.depth = var->bits_per_pixel;
+ display_info.pitch = (var->xres_virtual)*(var->bits_per_pixel)/8;
+ if (mac_var_to_vmode(var, &vmode, &cmode))
+ display_info.mode = 0;
+ else
+ display_info.mode = vmode;
+ strcpy(info->fb_info.modename, aty128fb_name);
+ display_info.fb_address = info->frame_buffer_phys;
+ display_info.cmap_adr_address = 0;
+ display_info.cmap_data_address = 0;
+ display_info.disp_reg_address = info->regbase_phys;
+ }
+#endif
+
return 0;
}
@@ -1275,24 +1384,29 @@
switch (bpp) {
#ifdef FBCON_HAS_CFB8
case 8:
- disp->dispsw = accel ? &fbcon_aty128_8 : &fbcon_cfb8;
+ info->dispsw = accel ? fbcon_aty128_8 : fbcon_cfb8;
+ disp->dispsw = &info->dispsw;
break;
#endif
#ifdef FBCON_HAS_CFB16
+ case 15:
case 16:
- disp->dispsw = &fbcon_cfb16;
+ info->dispsw = accel ? fbcon_aty128_16 : fbcon_cfb16;
+ disp->dispsw = &info->dispsw;
disp->dispsw_data = info->fbcon_cmap.cfb16;
break;
#endif
#ifdef FBCON_HAS_CFB24
case 24:
- disp->dispsw = &fbcon_cfb24;
+ info->dispsw = accel ? fbcon_aty128_24 : fbcon_cfb24;
+ disp->dispsw = &info->dispsw;
disp->dispsw_data = info->fbcon_cmap.cfb24;
break;
#endif
#ifdef FBCON_HAS_CFB32
case 32:
- disp->dispsw = &fbcon_cfb32;
+ info->dispsw = accel ? fbcon_aty128_32 : fbcon_cfb32;
+ disp->dispsw = &info->dispsw;
disp->dispsw_data = info->fbcon_cmap.cfb32;
break;
#endif
@@ -1310,21 +1424,23 @@
memset(fix, 0, sizeof(struct fb_fix_screeninfo));
strcpy(fix->id, aty128fb_name);
- fix->smem_start = (long) info->frame_buffer_phys;
- fix->smem_len = info->vram_size;
+ fix->smem_start = (long)info->frame_buffer_phys;
+ fix->smem_len = (u32)info->vram_size;
- fix->mmio_start = (long) info->regbase_phys;
+ fix->mmio_start = (long)info->regbase_phys;
fix->mmio_len = 0x1fff;
fix->type = FB_TYPE_PACKED_PIXELS;
+ fix->type_aux = 0;
fix->line_length = par->crtc.vxres*par->crtc.bpp/8;
fix->visual = par->crtc.bpp <= 8 ? FB_VISUAL_PSEUDOCOLOR
- : FB_VISUAL_DIRECTCOLOR;
-
+ : FB_VISUAL_DIRECTCOLOR;
+ fix->ywrapstep = 0;
fix->xpanstep = 8;
fix->ypanstep = 1;
fix->accel = FB_ACCEL_ATI_RAGE128;
+
return;
}
@@ -1344,6 +1460,7 @@
aty128_decode_var(&fb_display[con].var, &par, info);
aty128_encode_fix(fix, &par, info);
+
return 0;
}
@@ -1355,10 +1472,29 @@
*/
static int
aty128fb_pan_display(struct fb_var_screeninfo *var, int con,
- struct fb_info *info)
+ struct fb_info *fb)
{
- if (var->xoffset != 0 || var->yoffset != 0)
- return -EINVAL;
+ struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
+ struct aty128fb_par *par = &info->current_par;
+ u32 xoffset, yoffset;
+ u32 offset;
+ u32 xres, yres;
+
+ xres = (((par->crtc.h_total >> 16) & 0xff) + 1) * 8;
+ yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1;
+
+ xoffset = (var->xoffset +7) & ~7;
+ yoffset = var->yoffset;
+
+ if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres)
+ return -EINVAL;
+
+ par->crtc.xoffset = xoffset;
+ par->crtc.yoffset = yoffset;
+
+ offset = ((yoffset * par->crtc.vxres + xoffset) * par->crtc.bpp) >> 6;
+
+ aty_st_le32(CRTC_OFFSET, offset);
return 0;
}
@@ -1372,8 +1508,7 @@
aty128fb_get_cmap(struct fb_cmap *cmap, int kspc, int con,
struct fb_info *info)
{
- if (!info->display_fg ||
- con == info->display_fg->vc_num) /* current console ? */
+ if (con == currcon) /* current console? */
return fb_get_cmap(cmap, kspc, aty128_getcolreg, info);
else if (fb_display[con].cmap.len) /* non default colormap? */
fb_copy_cmap(&fb_display[con].cmap, cmap, kspc ? 0 : 2);
@@ -1381,6 +1516,7 @@
int size = (fb_display[con].var.bits_per_pixel <= 8) ? 256 : 32;
fb_copy_cmap(fb_default_cmap(size), cmap, kspc ? 0 : 2);
}
+
return 0;
}
@@ -1400,21 +1536,22 @@
else
disp = info->disp;
if (!disp->cmap.len) { /* no colormap allocated? */
- int size = (disp->var.bits_per_pixel <= 16) ? 256 : 32;
+ int size = (disp->var.bits_per_pixel <= 8) ? 256 : 32;
if ((err = fb_alloc_cmap(&disp->cmap, size, 0)))
return err;
}
- if (!info->display_fg || con == info->display_fg->vc_num)
-/* current console? */
+
+ if (con == currcon) /* current console? */
return fb_set_cmap(cmap, kspc, aty128_setcolreg, info);
else
fb_copy_cmap(cmap, &disp->cmap, kspc ? 0 : 1);
+
return 0;
}
/*
- * Virtual Frame Buffer Specific ioctls
+ * Frame Buffer Specific ioctls
*/
static int
@@ -1425,6 +1562,7 @@
}
+#ifndef MODULE
int __init
aty128fb_setup(char *options)
{
@@ -1445,9 +1583,17 @@
break;
memcpy(fontname, this_opt + 5, i);
fontname[i] = 0;
+ } else if (!strncmp(this_opt, "noaccel", 7)) {
+ noaccel = 1;
}
+#ifdef CONFIG_MTRR
+ else if(!strncmp(this_opt, "nomtrr", 6)) {
+ mtrr = 0;
+ }
+#endif /* CONFIG_MTRR */
#if defined(CONFIG_PPC)
- if (!strncmp(this_opt, "vmode:", 6)) {
+ /* vmode and cmode depreciated */
+ else if (!strncmp(this_opt, "vmode:", 6)) {
unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0);
if (vmode > 0 && vmode <= VMODE_MAX)
default_vmode = vmode;
@@ -1468,26 +1614,20 @@
break;
}
}
-#endif
-#ifdef CONFIG_MTRR
- if(mtrr) {
- ACCESS_FBINFO(mtrr.vram) =
- mtrr_add(video_base_phys, ACCESS_FBINFO(video.len),
- MTRR_TYPE_WRCOMB, 1);
- ACCESS_FBINFO(mtrr.valid_vram) = 1;
- printk(KERN_INFO "aty128fb: MTRR set to ON\n");
- }
-#endif
+#endif /* CONFIG_PPC */
+ else
+ mode_option = this_opt;
}
return 0;
}
+#endif /* !MODULE */
/*
* Initialisation
*/
-static int
+static int __init
aty128_init(struct fb_info_aty128 *info, const char *name)
{
struct fb_var_screeninfo var;
@@ -1496,7 +1636,7 @@
u8 chip_rev;
if (!register_test(info)) {
- printk("Can't write to video registers\n");
+ printk(KERN_ERR "Can't write to video registers\n");
return 0;
}
@@ -1505,44 +1645,14 @@
chip_rev = (aty_ld_le32(CONFIG_CNTL) >> 16) & 0x1F;
- /* TODO be more verbose */
- printk("aty128fb: Rage128 [rev 0x%x] ", chip_rev);
+ /* TODO: be more verbose */
+ printk(KERN_INFO "aty128fb: Rage128 [chip rev 0x%x] [card rev %x] ",
+ chip_rev, info->card_revision);
if (info->vram_size % (1024 * 1024) == 0)
- printk("%dM ", info->vram_size / (1024*1024));
+ printk("%dM \n", info->vram_size / (1024*1024));
else
- printk("%dk ", info->vram_size / 1024);
-
- var = default_var;
-
-#ifdef CONFIG_PMAC
-
- if (default_vmode == VMODE_NVRAM) {
-#ifdef CONFIG_NVRAM
- default_vmode = nvram_read_byte(NV_VMODE);
- if (default_vmode <= 0 || default_vmode > VMODE_MAX)
-#endif /* CONFIG_NVRAM */
- default_vmode = VMODE_CHOOSE;
- }
-
- if (default_cmode == CMODE_NVRAM) {
-#ifdef CONFIG_NVRAM
- default_cmode = nvram_read_byte(NV_CMODE);
- if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
-#endif /* CONFIG_NVRAM */
- default_vmode = VMODE_CHOOSE;
- }
-
- if (default_vmode != VMODE_CHOOSE &&
- mac_vmode_to_var(default_vmode, default_cmode, &var))
- var = default_var;
-
-#endif /* CONFIG_PMAC */
-
- if (aty128_decode_var(&var, &info->default_par, info)) {
- printk("Cannot set default mode.\n");
- return 0;
- }
+ printk("%dk \n", info->vram_size / 1024);
/* fill in info */
strcpy(info->fb_info.modename, aty128fb_name);
@@ -1555,6 +1665,39 @@
info->fb_info.blank = &aty128fbcon_blank;
info->fb_info.flags = FBINFO_FLAG_DEFAULT;
+#ifdef MODULE
+ var = default_var;
+#else
+ memset(&var, 0, sizeof(var));
+#ifdef CONFIG_PMAC
+ if (default_vmode == VMODE_CHOOSE) {
+ var = default_var;
+#endif /* CONFIG_PMAC */
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,1)
+ if (!fb_find_mode(&var, &info->fb_info, mode_option, NULL, 0,
+ &defaultmode, 8))
+ var = default_var;
+#endif
+
+#ifdef CONFIG_PMAC
+ } else {
+ if (mac_vmode_to_var(default_vmode, default_cmode, &var))
+ var = default_var;
+#endif /* CONFIG_PMAC */
+#endif /* MODULE */
+
+ if (noaccel)
+ var.accel_flags &= ~FB_ACCELF_TEXT;
+ else
+ var.accel_flags |= FB_ACCELF_TEXT;
+
+ if (aty128_decode_var(&var, &info->default_par, info)) {
+ printk(KERN_ERR "Cannot set default mode.\n");
+ return 0;
+ }
+
+ /* load up the palette with default colors */
for (j = 0; j < 16; j++) {
k = color_table[j];
info->palette[j].red = default_red[k];
@@ -1563,8 +1706,8 @@
}
dac = aty_ld_le32(DAC_CNTL) & 15; /* preserve lower three bits */
- dac |= DAC_8BIT_EN; /* set 8 bit dac */
- dac |= (0xFF << 24); /* set DAC mask */
+ dac |= DAC_8BIT_EN; /* set 8 bit dac */
+ dac |= DAC_MASK; /* set DAC mask */
aty_st_le32(DAC_CNTL, dac);
/* turn off bus mastering, just in case */
@@ -1573,116 +1716,179 @@
aty128fb_set_var(&var, -1, &info->fb_info);
aty128_init_engine(&info->default_par, info);
- printk("\n");
+ board_list = aty128_board_list_add(board_list, info);
+
if (register_framebuffer(&info->fb_info) < 0)
return 0;
- printk("fb%d: %s frame buffer device on %s\n",
+ printk(KERN_INFO "fb%d: %s frame buffer device on %s\n",
GET_FB_IDX(info->fb_info.node), aty128fb_name, name);
return 1; /* success! */
}
+/* add a new card to the list ++ajoshi */
+static struct
+fb_info_aty128 *aty128_board_list_add(struct fb_info_aty128 *board_list,
+ struct fb_info_aty128 *new_node)
+{
+ struct fb_info_aty128 *i_p = board_list;
+
+ new_node->next = NULL;
+ if(board_list == NULL)
+ return new_node;
+ while(i_p->next != NULL)
+ i_p = i_p->next;
+ i_p->next = new_node;
+
+ return board_list;
+}
+
+
void __init
aty128fb_init(void)
{
#if defined(CONFIG_FB_OF)
-/* let offb handle init */
+ /* let offb handle init */
#elif defined (CONFIG_PCI)
aty128pci_probe();
#endif
}
-void
+#ifndef CONFIG_FB_OF
+void __init
aty128pci_probe(void)
{
struct pci_dev *pdev = NULL;
- struct fb_info_aty128 *info;
- unsigned long fb_addr, reg_addr;
+ const struct aty128_chip_info *aci = &aty128_pci_probe_list[0];
+
+ while(aci->name != NULL) {
+ pdev = pci_find_device(aci->vendor, aci->device, NULL);
+ while(pdev != NULL) {
+ if(aty128_pci_register(pdev, aci) > 0)
+ return;
+ pdev = pci_find_device(aci->vendor, aci->device, pdev);
+ }
+ aci++;
+ }
+
+ return;
+}
+
+
+/* register a card ++ajoshi */
+static int __init
+aty128_pci_register(struct pci_dev *pdev,
+ const struct aty128_chip_info *aci)
+{
+ struct fb_info_aty128 *info = NULL;
+ unsigned long fb_addr, reg_addr = 0;
u16 tmp;
- while ((pdev = pci_find_device(PCI_VENDOR_ID_ATI, PCI_ANY_ID, pdev))) {
- if ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY) {
- struct resource *rp;
-
- /* FIXME add other known R128 device ID's */
- switch (pdev->device) {
- case 0x5245:
- case 0x5246:
- case 0x524B:
- case 0x524C:
- break;
- default:
- continue;
- }
-
- rp = &pdev->resource[0];
- fb_addr = rp->start;
- if (!fb_addr)
- continue;
- fb_addr &= PCI_BASE_ADDRESS_MEM_MASK;
-
- rp = &pdev->resource[2];
- reg_addr = rp->start;
- if (!reg_addr)
- continue;
- reg_addr &= PCI_BASE_ADDRESS_MEM_MASK;
-
- info = kmalloc(sizeof(struct fb_info_aty128), GFP_ATOMIC);
- if (!info) {
- printk("aty128fb: can't alloc fb_info_aty128\n");
- return;
- }
- memset(info, 0, sizeof(struct fb_info_aty128));
-
- info->regbase_phys = reg_addr;
- info->regbase = (unsigned long) ioremap(reg_addr, 0x1FFF);
-
- if (!info->regbase) {
- kfree(info);
- return;
- }
-
- info->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF;
-
- info->frame_buffer = fb_addr;
- info->frame_buffer = (unsigned long)
- ioremap(fb_addr, info->vram_size);
-
- if (!info->frame_buffer) {
- kfree(info);
- return;
- }
-
- pci_read_config_word(pdev, PCI_COMMAND, &tmp);
- if (!(tmp & PCI_COMMAND_MEMORY)) {
- tmp |= PCI_COMMAND_MEMORY;
- pci_write_config_word(pdev, PCI_COMMAND, tmp);
- }
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,1)
+ struct resource *rp;
-#if defined(CONFIG_PPC)
- aty128_timings(info);
+ rp = &pdev->resource[0];
+ fb_addr = rp->start;
+ fb_addr &= PCI_BASE_ADDRESS_MEM_MASK;
+
+ request_mem_region (rp->start, rp->end - rp->start + 1, "aty128fb");
+
+ rp = &pdev->resource[2];
+ reg_addr = rp->start;
+ reg_addr &= PCI_BASE_ADDRESS_MEM_MASK;
+
+ if (!reg_addr) {
+ release_mem_region (pdev->resource[0].start,
+ pdev->resource[0].end -
+ pdev->resource[0].start + 1);
+ return -1;
+ }
#else
- if (!aty128find_ROM(info)) {
- printk("Rage128 BIOS not located. Guessing...\n");
- aty128_timings(info);
- }
- else
- aty128_get_pllinfo(info);
+ fb_addr = pdev->base_address[0] & PCI_BASE_ADDRESS_MEM_MASK;
+ reg_addr = pdev->base_address[2] & PCI_BASE_ADDRESS_MEM_MASK;
+ if (!reg_addr)
+ return -1;
#endif
- if (!aty128_init(info, "PCI")) {
- kfree(info);
- return;
- }
- }
+ info = kmalloc(sizeof(struct fb_info_aty128), GFP_ATOMIC);
+ if(!info) {
+ printk(KERN_ERR "aty128fb: can't alloc fb_info_aty128\n");
+ goto unmap_out;
+ }
+ memset(info, 0, sizeof(struct fb_info_aty128));
+
+ info->pdev = pdev;
+
+ info->regbase_phys = reg_addr;
+ info->regbase = ioremap(reg_addr, 0x1FFF);
+
+ if (!info->regbase)
+ goto err_out;
+
+ pci_read_config_word(pdev, 0x08, &tmp);
+ info->card_revision = tmp;
+
+ info->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF;
+
+ info->frame_buffer_phys = fb_addr;
+ info->frame_buffer = (unsigned long)ioremap(fb_addr, info->vram_size);
+
+ if (!info->frame_buffer)
+ goto err_out;
+
+ pci_read_config_word(pdev, PCI_COMMAND, &tmp);
+ if (!(tmp & PCI_COMMAND_MEMORY)) {
+ tmp |= PCI_COMMAND_MEMORY;
+ pci_write_config_word(pdev, PCI_COMMAND, tmp);
+ }
+
+#if defined(CONFIG_PPC)
+ aty128_timings(info);
+#else
+ if (!aty128find_ROM(info)) {
+ printk(KERN_INFO "Rage128 BIOS not located. Guessing...\n");
+ aty128_timings(info);
}
+ else
+ aty128_get_pllinfo(info);
+#endif
+#ifdef CONFIG_MTRR
+ if (mtrr) {
+ info->mtrr.vram = mtrr_add(info->frame_buffer_phys, info->vram_size,
+ MTRR_TYPE_WRCOMB, 1);
+ info->mtrr.vram_valid = 1;
+ /* let there be speed */
+ printk(KERN_INFO "aty128fb: Rage128 MTRR set to ON\n");
+ }
+#endif /* CONFIG_MTRR */
+
+ if (!aty128_init(info, "PCI"))
+ goto err_out;
+
+ return 0;
+
+err_out:
+ kfree (info);
+unmap_out:
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,1)
+ release_mem_region (pdev->resource[0].start,
+ pdev->resource[0].end -
+ pdev->resource[0].start + 1);
+ release_mem_region (pdev->resource[2].start,
+ pdev->resource[2].end -
+ pdev->resource[2].start + 1);
+#endif
+
+ return -1;
}
+#endif /* ! CONFIG_FB_OF */
-static int
+#ifndef CONFIG_PPC
+static int __init
aty128find_ROM(struct fb_info_aty128 *info)
{
u32 segstart;
@@ -1691,20 +1897,18 @@
char *rom;
int stage;
int i;
- char aty_rom_sig[] = "761295520";
- char R128_sig[] = "R128";
+ char aty_rom_sig[] = "761295520"; /* ATI ROM Signature */
+ char R128_sig[] = "R128"; /* Rage128 ROM identifier */
int flag = 0;
-DBG("E aty128find_ROM");
- for (segstart = 0x000c0000; segstart < 0x000f0000; segstart += 0x00001000) {
+ for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
stage = 1;
rom_base = (char *) ioremap(segstart, 0x1000);
rom_base1 = (char *) (rom_base+1);
- if ((*rom_base == 0x55) && (((*rom_base1) & 0xff) == 0xaa)) {
+ if ((*rom_base == 0x55) && (((*rom_base1) & 0xff) == 0xaa))
stage = 2;
- }
if (stage != 2) {
iounmap(rom_base);
@@ -1726,6 +1930,7 @@
}
rom = rom_base;
+ /* ATI signature found. Let's see if it's a Rage128 */
for (i = 0; (i < 512) && (stage != 4); i++) {
if (R128_sig[0] == *rom) {
if (strncmp(R128_sig, rom, strlen(R128_sig)) == 0) {
@@ -1739,38 +1944,36 @@
continue;
}
- printk("Rage128 BIOS located at segment %4.4X\n", (u32)rom_base);
- info->BIOS_SEG = (u32)rom_base;
+ printk(KERN_INFO "aty128fb: Rage128 BIOS located at segment %4.4X\n",
+ (u32)rom_base);
+ info->BIOS_SEG = rom_base;
flag = 1;
-
break;
}
-DBG("L aty128find_ROM");
return (flag);
}
-static void
+static void __init
aty128_get_pllinfo(struct fb_info_aty128 *info)
{
- u32 bios_header;
- u32 *header_ptr;
+ void *bios_header;
+ void *header_ptr;
u16 bios_header_offset, pll_info_offset;
PLL_BLOCK pll;
-DBG("E aty128_get_pllinfo");
bios_header = info->BIOS_SEG + 0x48L;
- header_ptr = (u32 *)bios_header;
+ header_ptr = bios_header;
- bios_header_offset = (u16)*header_ptr;
- bios_header = info->BIOS_SEG + (u32)bios_header_offset;
+ bios_header_offset = readw(header_ptr);
+ bios_header = info->BIOS_SEG + bios_header_offset;
bios_header += 0x30;
- header_ptr = (u32 *)bios_header;
- pll_info_offset = (u16)*header_ptr;
- header_ptr = (u32 *)(info->BIOS_SEG + (u32)pll_info_offset);
+ header_ptr = bios_header;
+ pll_info_offset = readw(header_ptr);
+ header_ptr = info->BIOS_SEG + pll_info_offset;
- memcpy(&pll, header_ptr, 50);
+ memcpy_fromio(&pll, header_ptr, 50);
info->constants.ppll_max = pll.PCLK_max_freq;
info->constants.ppll_min = pll.PCLK_min_freq;
@@ -1778,9 +1981,20 @@
info->constants.ref_divider = (u32)pll.PCLK_ref_divider;
info->constants.dotclock = (u32)pll.PCLK_ref_freq;
+ aty_st_pll(PPLL_REF_DIV, info->constants.ref_divider);
+ aty_pll_writeupdate(info);
+
info->constants.fifo_width = 128;
info->constants.fifo_depth = 32;
+#ifdef DEBUG
+ printk(KERN_DEBUG "get_pllinfo: ppll_max %d ppll_min %d xclk %d "
+ "ref_divider %d dotclock %d\n",
+ info->constants.ppll_max, info->constants.ppll_min,
+ info->constants.xclk, info->constants.ref_divider,
+ info->constants.dotclock);
+#endif
+
switch(aty_ld_le32(MEM_CNTL) & 0x03) {
case 0:
info->mem = &sdr_128;
@@ -1795,13 +2009,17 @@
info->mem = &sdr_sgram;
}
-DBG("L aty128get_pllinfo");
+ /* free up to-be unused resources */
+ if (info->BIOS_SEG)
+ iounmap(info->BIOS_SEG);
+
return;
}
+#endif /* ! CONFIG_PPC */
#ifdef CONFIG_FB_OF
-void
+void __init
aty128fb_of_init(struct device_node *dp)
{
unsigned long addr, reg_addr, fb_addr;
@@ -1815,25 +2033,25 @@
reg_addr = dp->addrs[2].address;
break;
default:
- printk("aty128fb: TODO unexpected addresses\n");
+ printk(KERN_ERR "aty128fb: TODO unexpected addresses\n");
return;
}
addr = (unsigned long) ioremap(reg_addr, 0x1FFF);
if (!addr) {
- printk("aty128fb: can't map memory registers\n");
+ printk(KERN_ERR "aty128fb: can't map memory registers\n");
return;
}
info = kmalloc(sizeof(struct fb_info_aty128), GFP_ATOMIC);
if (!info) {
- printk("aty128fb: can't alloc fb_info_aty128\n");
+ printk(KERN_ERR "aty128fb: can't alloc fb_info_aty128\n");
return;
}
- memset(info, 0, sizeof(struct fb_info_aty128));
+ memset((void *) info, 0, sizeof(struct fb_info_aty128));
info->regbase_phys = reg_addr;
- info->regbase = addr;
+ info->regbase = (void *) addr;
/* enabled memory-space accesses using config-space command register */
if (pci_device_loc(dp, &bus, &devfn) == 0) {
@@ -1846,45 +2064,48 @@
info->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF;
info->frame_buffer_phys = fb_addr;
- info->frame_buffer = (unsigned long) ioremap(fb_addr, info->vram_size);
-
- /*
- * TODO find OF values/hints.
- *
- * If we are booted from BootX, the MacOS ATI driver will likely have
- * left useful tidbits in the DeviceRegistry.
- */
+ info->frame_buffer = (void *) ioremap(fb_addr, info->vram_size);
if (!info->frame_buffer) {
- printk("aty128fb: can't map frame buffer\n");
- return;
+ printk(KERN_ERR "aty128fb: can't map frame buffer\n");
+ kfree(info);
+ return;
}
+ /* fall back to defaults */
aty128_timings(info);
if (!aty128_init(info, dp->full_name)) {
kfree(info);
return;
}
-}
+
+#ifdef CONFIG_FB_COMPAT_XPMAC
+ if (!console_fb_info)
+ console_fb_info = &info->fb_info;
#endif
+}
+#endif /* CONFIG_FB_OF */
/* fill in known card constants if pll_block is not available */
-static void
+static void __init
aty128_timings(struct fb_info_aty128 *info)
{
/* TODO make an attempt at probing */
-
- info->constants.dotclock = 2950;
+ if (!info->constants.dotclock)
+ info->constants.dotclock = 2950;
/* from documentation */
- info->constants.ppll_min = 12500;
- info->constants.ppll_max = 25000; /* 23000 on some cards? */
+ if (!info->constants.ppll_min)
+ info->constants.ppll_min = 12500;
+ if (!info->constants.ppll_max)
+ info->constants.ppll_max = 25000; /* 23000 on some cards? */
#if 1
- /* XXX TODO. Calculate properly. Fix OF's pll ideas. */
- info->constants.ref_divider = 0x3b;
+ /* XXX TODO. Calculuate properly. Fix OF's pll ideas. */
+ if (!info->constants.ref_divider)
+ info->constants.ref_divider = 0x3b;
aty_st_pll(PPLL_REF_DIV, info->constants.ref_divider);
aty_pll_writeupdate(info);
@@ -1895,7 +2116,8 @@
#endif
/* TODO. Calculate */
- info->constants.xclk = 0x1d4d; /* same as mclk */
+ if (!info->constants.xclk)
+ info->constants.xclk = 0x1d4d; /* same as mclk */
info->constants.fifo_width = 128;
info->constants.fifo_depth = 32;
@@ -1919,27 +2141,23 @@
static int
aty128fbcon_switch(int con, struct fb_info *fb)
{
- currcon = con;
+ struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
+ struct aty128fb_par par;
/* Do we have to save the colormap? */
if (fb_display[currcon].cmap.len)
- fb_get_cmap(&fb_display[currcon].cmap, 1, aty128_getcolreg, fb);
+ fb_get_cmap(&fb_display[currcon].cmap, 1, aty128_getcolreg, fb);
-#if 1
- aty128fb_set_var(&fb_display[con].var, con, fb);
-#else
-{
- struct fb_info_aty128 *info = (struct fb_info_aty128 *) fb;
- struct aty128fb_par par;
+ /* set the current console */
+ currcon = con;
aty128_decode_var(&fb_display[con].var, &par, info);
aty128_set_par(&par, info);
- aty128_set_disp(&fb_display[con], info,
- fb_display[con].var.bits_per_pixel);
+
+ aty128_set_disp(&fb_display[con], info, par.crtc.bpp,
+ par.accel_flags & FB_ACCELF_TEXT);
do_install_cmap(con, fb);
-}
-#endif
return 1;
}
@@ -1948,7 +2166,6 @@
/*
* Blank the display.
*/
-
static void
aty128fbcon_blank(int blank, struct fb_info *fb)
{
@@ -1983,6 +2200,7 @@
*green = (info->palette[regno].green<<8) | info->palette[regno].green;
*blue = (info->palette[regno].blue<<8) | info->palette[regno].blue;
*transp = 0;
+
return 0;
}
@@ -1996,7 +2214,7 @@
aty128_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *fb)
{
- struct fb_info_aty128 *info = (struct fb_info_aty128 *) fb;
+ struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
u32 col;
if (regno > 255)
@@ -2009,32 +2227,47 @@
info->palette[regno].green = green;
info->palette[regno].blue = blue;
- aty_st_8(PALETTE_INDEX, regno);
- col = red << 16 | green << 8 | blue;
+ /* initialize gamma ramp for hi-color+ */
+ if ((info->current_par.crtc.bpp > 8) && (regno == 0)) {
+ int i;
+
+ for (i=16; i<256; i++) {
+ aty_st_8(PALETTE_INDEX, i);
+ col = (i << 16) | (i << 8) | i;
+ aty_st_le32(PALETTE_DATA, col);
+ }
+ }
+
+ /* initialize palette */
+ if (info->current_par.crtc.bpp == 16)
+ aty_st_8(PALETTE_INDEX, (regno << 3));
+ else
+ aty_st_8(PALETTE_INDEX, regno);
+ col = (red << 16) | (green << 8) | blue;
aty_st_le32(PALETTE_DATA, col);
if (regno < 16)
switch (info->current_par.crtc.bpp) {
#ifdef FBCON_HAS_CFB16
- case 16:
+ case 9 ... 16:
info->fbcon_cmap.cfb16[regno] = (regno << 10) | (regno << 5) |
- regno;
+ regno;
break;
#endif
#ifdef FBCON_HAS_CFB24
- case 24:
+ case 17 ... 24:
info->fbcon_cmap.cfb24[regno] = (regno << 16) | (regno << 8) |
regno;
break;
#endif
#ifdef FBCON_HAS_CFB32
- case 32:
- {
- u32 i;
- i = (regno << 8) | regno;
- info->fbcon_cmap.cfb32[regno] = (i << 16) | i;
- }
+ case 25 ... 32: {
+ u32 i;
+
+ i = (regno << 8) | regno;
+ info->fbcon_cmap.cfb32[regno] = (i << 16) | i;
break;
+ }
#endif
}
return 0;
@@ -2046,6 +2279,7 @@
{
if (con != currcon)
return;
+
if (fb_display[con].cmap.len)
fb_set_cmap(&fb_display[con].cmap, 1, aty128_setcolreg, info);
else {
@@ -2063,10 +2297,12 @@
aty128_rectdraw(s16 x, s16 y, u16 width, u16 height,
struct fb_info_aty128 *info)
{
- /* perform rectangle fill */
+ /* perform rectangle operation */
wait_for_fifo(2, info);
aty_st_le32(DST_Y_X, (y << 16) | x);
aty_st_le32(DST_HEIGHT_WIDTH, (height << 16) | width);
+
+ info->blitter_may_be_busy = 1;
}
@@ -2075,42 +2311,35 @@
u_int width, u_int height,
struct fb_info_aty128 *info)
{
- u32 direction = DST_LAST_PEL;
- u32 pitch_value;
-
- if (!width || !height)
- return;
+ u32 save_dp_datatype, save_dp_cntl;
- pitch_value = info->current_par.crtc.vxres;
- if (info->current_par.crtc.bpp == 24) {
- /* In 24 bpp, the engine is in 8 bpp - this requires that all */
- /* horizontal coordinates and widths must be adjusted */
- pitch_value *= 3;
- srcx *= 3;
- dstx *= 3;
- width *= 3;
- }
-
- if (srcy < dsty) {
- dsty += height - 1;
- srcy += height - 1;
- } else
- direction |= DST_Y_TOP_TO_BOTTOM;
-
- if (srcx < dstx) {
- dstx += width - 1;
- srcx += width - 1;
- } else
- direction |= DST_X_LEFT_TO_RIGHT;
+ wait_for_fifo(2, info);
+ save_dp_datatype = aty_ld_le32(DP_DATATYPE);
+ save_dp_cntl = aty_ld_le32(DP_CNTL);
- wait_for_fifo(4, info);
- aty_st_le32(SRC_Y_X, (srcy << 16) | srcx);
+ wait_for_fifo(6, info);
+ aty_st_le32(DP_DATATYPE, (0 | BRUSH_SOLIDCOLOR << 16) | SRC_DSTCOLOR);
aty_st_le32(DP_MIX, ROP3_SRCCOPY | DP_SRC_RECT);
- aty_st_le32(DP_CNTL, direction);
- aty_st_le32(DP_DATATYPE, aty_ld_le32(DP_DATATYPE) | SRC_DSTCOLOR);
- aty128_rectdraw(dstx, dsty, width, height, info);
+ aty_st_le32(DP_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
+ aty_st_le32(SRC_Y_X, (srcy << 16) | srcx);
+ aty_st_le32(DST_Y_X, (dsty << 16) | dstx);
+ aty_st_le32(DST_HEIGHT_WIDTH, (height << 16) | width);
+
+ wait_for_fifo(2, info);
+ aty_st_le32(DP_DATATYPE, save_dp_datatype);
+ aty_st_le32(DP_CNTL, save_dp_cntl);
+
+ info->blitter_may_be_busy = 1;
+
+ wait_for_idle(info);
}
+
+ /*
+ * Text mode accelerated functions
+ */
+
+
static void
fbcon_aty128_bmove(struct display *p, int sy, int sx, int dy, int dx,
int height, int width)
@@ -2126,25 +2355,225 @@
(struct fb_info_aty128 *)p->fb_info);
}
+
+/* TODO: Fix accel and add to these structs */
#ifdef FBCON_HAS_CFB8
+static void fbcon_aty8_putc(struct vc_data *conp, struct display *p,
+ int c, int yy, int xx)
+{
+ struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
+
+ if (fb->blitter_may_be_busy)
+ wait_for_idle(fb);
+
+ fbcon_cfb8_putc(conp, p, c, yy, xx);
+}
+
+
+static void fbcon_aty8_putcs(struct vc_data *conp, struct display *p,
+ const unsigned short *s, int count,
+ int yy, int xx)
+{
+ struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
+
+ if (fb->blitter_may_be_busy)
+ wait_for_idle(fb);
+
+ fbcon_cfb8_putcs(conp, p, s, count, yy, xx);
+}
+
+
+static void fbcon_aty8_clear_margins(struct vc_data *conp,
+ struct display *p, int bottom_only)
+{
+ struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
+
+ if (fb->blitter_may_be_busy)
+ wait_for_idle(fb);
+
+ fbcon_cfb8_clear_margins(conp, p, bottom_only);
+}
+
static struct display_switch fbcon_aty128_8 = {
- fbcon_cfb8_setup, fbcon_aty128_bmove, fbcon_cfb8_clear, fbcon_cfb8_putc,
- fbcon_cfb8_putcs, fbcon_cfb8_revc, NULL, NULL, fbcon_cfb8_clear_margins,
+ fbcon_cfb8_setup, fbcon_aty128_bmove, fbcon_cfb8_clear,
+ fbcon_aty8_putc, fbcon_aty8_putcs, fbcon_cfb8_revc, NULL, NULL,
+ fbcon_aty8_clear_margins,
+ FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
+};
+#endif
+#ifdef FBCON_HAS_CFB16
+static void fbcon_aty16_putc(struct vc_data *conp, struct display *p,
+ int c, int yy, int xx)
+{
+ struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
+
+ if (fb->blitter_may_be_busy)
+ wait_for_idle(fb);
+
+ fbcon_cfb16_putc(conp, p, c, yy, xx);
+}
+
+
+static void fbcon_aty16_putcs(struct vc_data *conp, struct display *p,
+ const unsigned short *s, int count,
+ int yy, int xx)
+{
+ struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
+
+ if (fb->blitter_may_be_busy)
+ wait_for_idle(fb);
+
+ fbcon_cfb16_putcs(conp, p, s, count, yy, xx);
+}
+
+
+static void fbcon_aty16_clear_margins(struct vc_data *conp,
+ struct display *p, int bottom_only)
+{
+ struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
+
+ if (fb->blitter_may_be_busy)
+ wait_for_idle(fb);
+
+ fbcon_cfb16_clear_margins(conp, p, bottom_only);
+}
+
+static struct display_switch fbcon_aty128_16 = {
+ fbcon_cfb16_setup, fbcon_aty128_bmove, fbcon_cfb16_clear,
+ fbcon_aty16_putc, fbcon_aty16_putcs, fbcon_cfb16_revc, NULL, NULL,
+ fbcon_aty16_clear_margins,
+ FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
+};
+#endif
+#ifdef FBCON_HAS_CFB24
+static void fbcon_aty24_putc(struct vc_data *conp, struct display *p,
+ int c, int yy, int xx)
+{
+ struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
+
+ if (fb->blitter_may_be_busy)
+ wait_for_idle(fb);
+
+ fbcon_cfb24_putc(conp, p, c, yy, xx);
+}
+
+
+static void fbcon_aty24_putcs(struct vc_data *conp, struct display *p,
+ const unsigned short *s, int count,
+ int yy, int xx)
+{
+ struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
+
+ if (fb->blitter_may_be_busy)
+ wait_for_idle(fb);
+
+ fbcon_cfb24_putcs(conp, p, s, count, yy, xx);
+}
+
+
+static void fbcon_aty24_clear_margins(struct vc_data *conp,
+ struct display *p, int bottom_only)
+{
+ struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
+
+ if (fb->blitter_may_be_busy)
+ wait_for_idle(fb);
+
+ fbcon_cfb24_clear_margins(conp, p, bottom_only);
+}
+
+static struct display_switch fbcon_aty128_24 = {
+ fbcon_cfb24_setup, fbcon_aty128_bmove, fbcon_cfb24_clear,
+ fbcon_aty24_putc, fbcon_aty24_putcs, fbcon_cfb24_revc, NULL, NULL,
+ fbcon_aty24_clear_margins,
+ FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
+};
+#endif
+#ifdef FBCON_HAS_CFB32
+static void fbcon_aty32_putc(struct vc_data *conp, struct display *p,
+ int c, int yy, int xx)
+{
+ struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
+
+ if (fb->blitter_may_be_busy)
+ wait_for_idle(fb);
+
+ fbcon_cfb32_putc(conp, p, c, yy, xx);
+}
+
+
+static void fbcon_aty32_putcs(struct vc_data *conp, struct display *p,
+ const unsigned short *s, int count,
+ int yy, int xx)
+{
+ struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
+
+ if (fb->blitter_may_be_busy)
+ wait_for_idle(fb);
+
+ fbcon_cfb32_putcs(conp, p, s, count, yy, xx);
+}
+
+
+static void fbcon_aty32_clear_margins(struct vc_data *conp,
+ struct display *p, int bottom_only)
+{
+ struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
+
+ if (fb->blitter_may_be_busy)
+ wait_for_idle(fb);
+
+ fbcon_cfb32_clear_margins(conp, p, bottom_only);
+}
+
+static struct display_switch fbcon_aty128_32 = {
+ fbcon_cfb32_setup, fbcon_aty128_bmove, fbcon_cfb32_clear,
+ fbcon_aty32_putc, fbcon_aty32_putcs, fbcon_cfb32_revc, NULL, NULL,
+ fbcon_aty32_clear_margins,
FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
};
#endif
-#if defined(MODULE) && defined(DEBUG)
-int
+#if defined(MODULE)
+MODULE_AUTHOR("(c)1999-2000 Brad Douglas <brad@neruo.com>, Anthony Tong "
+ "<atong@uiuc.edu>");
+MODULE_DESCRIPTION("FBDev driver for ATI Rage128 cards");
+
+int __init
init_module(void)
{
aty128pci_probe();
return 0;
}
-void
+void __exit
cleanup_module(void)
{
-/* XXX unregister! */
+ struct fb_info_aty128 *info = board_list;
+
+ while (board_list) {
+ info = board_list;
+ board_list = board_list->next;
+
+ unregister_framebuffer(&info->fb_info);
+#ifdef CONFIG_MTRR
+ if (info->mtrr.vram_valid)
+ mtrr_del(info->mtrr.vram, info->frame_buffer_phys,
+ info->vram_size);
+#endif /* CONFIG_MTRR */
+ iounmap(info->regbase);
+ iounmap(&info->frame_buffer);
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,1)
+ release_mem_region(info->pdev->resource[0].start,
+ info->pdev->resource[0].end -
+ info->pdev->resource[0].start + 1);
+ release_mem_region(info->pdev->resource[2].start,
+ info->pdev->resource[2].end -
+ info->pdev->resource[2].start + 1);
+#endif
+
+ kfree(info);
+ }
}
#endif /* MODULE */
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TCL-scripts by Sam Shen (who was at: slshen@lbl.gov)