patch-2.3.48 linux/arch/mips/mm/andes.c

• Lines: 182
• Date: Thu Feb 24 22:52:30 2000
• Orig file: v2.3.47/linux/arch/mips/mm/andes.c
• Orig date: Tue Aug 31 17:29:12 1999

diff -u --recursive --new-file v2.3.47/linux/arch/mips/mm/andes.c linux/arch/mips/mm/andes.c
@@ -1,4 +1,4 @@
-/* $Id: andes.c,v 1.6 1999/01/04 16:03:52 ralf Exp $
+/* $Id: andes.c,v 1.11 2000/02/24 00:12:40 ralf Exp $
  *
  * andes.c: MMU and cache operations for the R10000 (ANDES).
  *
@@ -14,7 +14,82 @@
 #include <asm/sgialib.h>
 #include <asm/mmu_context.h>
 
-extern unsigned long mips_tlb_entries;
+/* page functions */
+void andes_clear_page(void * page)
+{
+	__asm__ __volatile__(
+		".set\tnoreorder\n\t"
+		".set\tnoat\n\t"
+		"addiu\t$1,%0,%2\n"
+		"1:\tsw\t$0,(%0)\n\t"
+		"sw\t$0,4(%0)\n\t"
+		"sw\t$0,8(%0)\n\t"
+		"sw\t$0,12(%0)\n\t"
+		"addiu\t%0,32\n\t"
+		"sw\t$0,-16(%0)\n\t"
+		"sw\t$0,-12(%0)\n\t"
+		"sw\t$0,-8(%0)\n\t"
+		"bne\t$1,%0,1b\n\t"
+		"sw\t$0,-4(%0)\n\t"
+		".set\tat\n\t"
+		".set\treorder"
+		:"=r" (page)
+		:"0" (page),
+		 "I" (PAGE_SIZE)
+		:"$1","memory");
+}
+
+static void andes_copy_page(void * to, void * from)
+{
+	unsigned long dummy1, dummy2;
+	unsigned long reg1, reg2, reg3, reg4;
+
+	__asm__ __volatile__(
+		".set\tnoreorder\n\t"
+		".set\tnoat\n\t"
+		"addiu\t$1,%0,%8\n"
+		"1:\tlw\t%2,(%1)\n\t"
+		"lw\t%3,4(%1)\n\t"
+		"lw\t%4,8(%1)\n\t"
+		"lw\t%5,12(%1)\n\t"
+		"sw\t%2,(%0)\n\t"
+		"sw\t%3,4(%0)\n\t"
+		"sw\t%4,8(%0)\n\t"
+		"sw\t%5,12(%0)\n\t"
+		"lw\t%2,16(%1)\n\t"
+		"lw\t%3,20(%1)\n\t"
+		"lw\t%4,24(%1)\n\t"
+		"lw\t%5,28(%1)\n\t"
+		"sw\t%2,16(%0)\n\t"
+		"sw\t%3,20(%0)\n\t"
+		"sw\t%4,24(%0)\n\t"
+		"sw\t%5,28(%0)\n\t"
+		"addiu\t%0,64\n\t"
+		"addiu\t%1,64\n\t"
+		"lw\t%2,-32(%1)\n\t"
+		"lw\t%3,-28(%1)\n\t"
+		"lw\t%4,-24(%1)\n\t"
+		"lw\t%5,-20(%1)\n\t"
+		"sw\t%2,-32(%0)\n\t"
+		"sw\t%3,-28(%0)\n\t"
+		"sw\t%4,-24(%0)\n\t"
+		"sw\t%5,-20(%0)\n\t"
+		"lw\t%2,-16(%1)\n\t"
+		"lw\t%3,-12(%1)\n\t"
+		"lw\t%4,-8(%1)\n\t"
+		"lw\t%5,-4(%1)\n\t"
+		"sw\t%2,-16(%0)\n\t"
+		"sw\t%3,-12(%0)\n\t"
+		"sw\t%4,-8(%0)\n\t"
+		"bne\t$1,%0,1b\n\t"
+		"sw\t%5,-4(%0)\n\t"
+		".set\tat\n\t"
+		".set\treorder"
+		:"=r" (dummy1), "=r" (dummy2),
+		 "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
+		:"0" (to), "1" (from),
+		 "I" (PAGE_SIZE));
+}
 
 /* Cache operations. XXX Write these dave... */
 static inline void andes_flush_cache_all(void)
@@ -40,7 +115,7 @@
 	/* XXX */
 }
 
-static void andes_flush_page_to_ram(unsigned long page)
+static void andes_flush_page_to_ram(struct page * page)
 {
 	/* XXX */
 }
@@ -51,67 +126,52 @@
 }
 
 /* TLB operations. XXX Write these dave... */
-static inline void andes_flush_tlb_all(void)
+void flush_tlb_all(void)
 {
 	/* XXX */
 }
 
-static void andes_flush_tlb_mm(struct mm_struct *mm)
+void flush_tlb_mm(struct mm_struct *mm)
 {
 	/* XXX */
 }
 
-static void andes_flush_tlb_range(struct mm_struct *mm, unsigned long start,
+void flush_tlb_range(struct mm_struct *mm, unsigned long start,
 				  unsigned long end)
 {
 	/* XXX */
 }
 
-static void andes_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
+void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 {
 	/* XXX */
 }
 
-static void andes_load_pgd(unsigned long pg_dir)
+void load_pgd(unsigned long pg_dir)
 {
 }
 
-static void andes_pgd_init(unsigned long page)
+void pgd_init(unsigned long page)
 {
 }
 
-static void andes_add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
+void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
 				  unsigned long entryhi, unsigned long pagemask)
 {
         /* XXX */
 }
 
-static int andes_user_mode(struct pt_regs *regs)
-{
-	return (regs->cp0_status & ST0_KSU) == KSU_USER;
-}
-
 void __init ld_mmu_andes(void)
 {
-	flush_cache_all = andes_flush_cache_all;
-	flush_cache_mm = andes_flush_cache_mm;
-	flush_cache_range = andes_flush_cache_range;
-	flush_cache_page = andes_flush_cache_page;
-	flush_cache_sigtramp = andes_flush_cache_sigtramp;
-	flush_page_to_ram = andes_flush_page_to_ram;
-
-	flush_tlb_all = andes_flush_tlb_all;
-	flush_tlb_mm = andes_flush_tlb_mm;
-	flush_tlb_range = andes_flush_tlb_range;
-	flush_tlb_page = andes_flush_tlb_page;
-	andes_asid_setup();
-    
-        add_wired_entry = andes_add_wired_entry;
-
-	user_mode = andes_user_mode;
+	_clear_page = andes_clear_page;
+	_copy_page = andes_copy_page;
 
-	load_pgd = andes_load_pgd;
-	pgd_init = andes_pgd_init;
+	_flush_cache_all = andes_flush_cache_all;
+	_flush_cache_mm = andes_flush_cache_mm;
+	_flush_cache_range = andes_flush_cache_range;
+	_flush_cache_page = andes_flush_cache_page;
+	_flush_cache_sigtramp = andes_flush_cache_sigtramp;
+	_flush_page_to_ram = andes_flush_page_to_ram;
 
 	flush_cache_all();
 	flush_tlb_all();