# frv testcase for csdiv $GRi,$GRj,$GRk,$CCi,$cond # mach: all .include "testutils.inc" start .global csdiv csdiv: set_spr_immed 0x1b1b,cccr ; simple division 12 / 3 set_gr_immed 3,gr3 set_gr_immed 12,gr1 csdiv gr1,gr3,gr2,cc4,1 test_gr_immed 4,gr2 ; Random example set_gr_limmed 0x0123,0x4567,gr3 set_gr_limmed 0xfedc,0xba98,gr1 csdiv gr1,gr3,gr2,cc4,1 test_gr_immed -1,gr2 ; Special case from the Arch Spec Vol 2 and_spr_immed -33,isr ; turn off isr.edem ; set up exception handler set_psr_et 1 and_spr_immed -4081,tbr ; clear tbr.tt set_gr_spr tbr,gr17 inc_gr_immed 0x170,gr17 ; address of exception handler set_bctrlr_0_0 gr17 set_spr_immed 128,lcr set_gr_immed 0,gr15 ; divide will cause overflow set_spr_addr ok1,lr set_gr_addr e1,gr17 set_gr_immed -1,gr3 set_gr_limmed 0x8000,0x0000,gr1 e1: csdiv gr1,gr3,gr2,cc4,1 test_gr_immed 1,gr15 test_gr_limmed 0x8000,0x0000,gr2 ; Special case from the Arch Spec Vol 2 or_spr_immed 0x20,isr ; turn on isr.edem set_gr_immed -1,gr3 set_gr_limmed 0x8000,0x0000,gr1 csdiv gr1,gr3,gr2,cc4,1 test_gr_limmed 0x7fff,0xffff,gr2 ; simple division 12 / 3 set_gr_immed 3,gr3 set_gr_immed 12,gr1 csdiv gr1,gr3,gr2,cc4,0 test_gr_limmed 0x7fff,0xffff,gr2 ; Random example set_gr_limmed 0x0123,0x4567,gr3 set_gr_limmed 0xfedc,0xba98,gr1 csdiv gr1,gr3,gr2,cc4,0 test_gr_limmed 0x7fff,0xffff,gr2 ; Special case from the Arch Spec Vol 2 and_spr_immed -33,isr ; turn off isr.edem set_gr_immed -1,gr3 set_gr_limmed 0x8000,0x0000,gr1 csdiv gr1,gr3,gr2,cc4,0 test_gr_limmed 0x7fff,0xffff,gr2 or_spr_immed 0x20,isr ; turn on isr.edem set_gr_immed -1,gr3 set_gr_limmed 0x8000,0x0000,gr1 csdiv gr1,gr3,gr2,cc4,0 test_gr_limmed 0x7fff,0xffff,gr2 ; simple division 12 / 3 set_gr_immed 3,gr3 set_gr_immed 12,gr1 csdiv gr1,gr3,gr2,cc5,0 test_gr_immed 4,gr2 ; Random example set_gr_limmed 0x0123,0x4567,gr3 set_gr_limmed 0xfedc,0xba98,gr1 csdiv gr1,gr3,gr2,cc5,0 test_gr_immed -1,gr2 ; Special case from the Arch Spec Vol 2 and_spr_immed -33,isr ; turn off isr.edem ; divide will cause overflow set_spr_addr ok1,lr set_gr_addr e2,gr17 set_gr_immed -1,gr3 set_gr_limmed 0x8000,0x0000,gr1 e2: csdiv gr1,gr3,gr2,cc5,0 test_gr_immed 2,gr15 test_gr_limmed 0x8000,0x0000,gr2 ; Special case from the Arch Spec Vol 2 or_spr_immed 0x20,isr ; turn on isr.edem set_gr_immed -1,gr3 set_gr_limmed 0x8000,0x0000,gr1 csdiv gr1,gr3,gr2,cc5,0 test_gr_limmed 0x7fff,0xffff,gr2 ; simple division 12 / 3 set_gr_immed 3,gr3 set_gr_immed 12,gr1 csdiv gr1,gr3,gr2,cc5,1 test_gr_limmed 0x7fff,0xffff,gr2 ; Random example set_gr_limmed 0x0123,0x4567,gr3 set_gr_limmed 0xfedc,0xba98,gr1 csdiv gr1,gr3,gr2,cc5,1 test_gr_limmed 0x7fff,0xffff,gr2 ; Special case from the Arch Spec Vol 2 and_spr_immed -33,isr ; turn off isr.edem set_gr_immed -1,gr3 set_gr_limmed 0x8000,0x0000,gr1 csdiv gr1,gr3,gr2,cc5,1 test_gr_limmed 0x7fff,0xffff,gr2 or_spr_immed 0x20,isr ; turn on isr.edem set_gr_immed -1,gr3 set_gr_limmed 0x8000,0x0000,gr1 csdiv gr1,gr3,gr2,cc5,1 test_gr_limmed 0x7fff,0xffff,gr2 ; simple division 12 / 3 set_gr_immed 3,gr3 set_gr_immed 12,gr1 csdiv gr1,gr3,gr2,cc6,0 test_gr_limmed 0x7fff,0xffff,gr2 ; Random example set_gr_limmed 0x0123,0x4567,gr3 set_gr_limmed 0xfedc,0xba98,gr1 csdiv gr1,gr3,gr2,cc6,0 test_gr_limmed 0x7fff,0xffff,gr2 ; Special case from the Arch Spec Vol 2 and_spr_immed -33,isr ; turn off isr.edem set_gr_immed -1,gr3 set_gr_limmed 0x8000,0x0000,gr1 csdiv gr1,gr3,gr2,cc6,0 test_gr_limmed 0x7fff,0xffff,gr2 or_spr_immed 0x20,isr ; turn on isr.edem set_gr_immed -1,gr3 set_gr_limmed 0x8000,0x0000,gr1 csdiv gr1,gr3,gr2,cc6,0 test_gr_limmed 0x7fff,0xffff,gr2 ; simple division 12 / 3 set_gr_immed 3,gr3 set_gr_immed 12,gr1 csdiv gr1,gr3,gr2,cc7,1 test_gr_limmed 0x7fff,0xffff,gr2 ; Random example set_gr_limmed 0x0123,0x4567,gr3 set_gr_limmed 0xfedc,0xba98,gr1 csdiv gr1,gr3,gr2,cc7,1 test_gr_limmed 0x7fff,0xffff,gr2 ; Special case from the Arch Spec Vol 2 and_spr_immed -33,isr ; turn off isr.edem set_gr_immed -1,gr3 set_gr_limmed 0x8000,0x0000,gr1 csdiv gr1,gr3,gr2,cc7,1 test_gr_limmed 0x7fff,0xffff,gr2 or_spr_immed 0x20,isr ; turn on isr.edem set_gr_immed -1,gr3 set_gr_limmed 0x8000,0x0000,gr1 csdiv gr1,gr3,gr2,cc7,1 test_gr_limmed 0x7fff,0xffff,gr2 pass ok1: ; exception handler for overflow test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set test_spr_gr epcr0,gr17 ; return address set test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set inc_gr_immed 1,gr15 rett 0 fail