1/*
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $Id: ar5416phy.h,v 1.3 2011/03/07 11:25:44 cegger Exp $
18 */
19#ifndef _DEV_ATH_AR5416PHY_H_
20#define _DEV_ATH_AR5416PHY_H_
21
22#include "ar5212/ar5212phy.h"
23
24#define AR_PHY_CHIP_ID_REV_0 0x80 /* 5416 Rev 0 (owl 1.0) BB */
25#define AR_PHY_CHIP_ID_REV_1 0x81 /* 5416 Rev 1 (owl 2.0) BB */
26
27#define RFSILENT_BB 0x00002000 /* shush bb */
28#define AR_PHY_RESTART 0x9970 /* restart */
29#define AR_PHY_RESTART_DIV_GC 0x001C0000 /* bb_ant_fast_div_gc_limit */
30#define AR_PHY_RESTART_DIV_GC_S 18
31
32/* PLL settling times */
33#define RTC_PLL_SETTLE_DELAY 1000 /* 1 ms */
34#define HT40_CHANNEL_CENTER_SHIFT 10 /* MHz */
35
36#define AR_PHY_RFBUS_REQ 0x997C
37#define AR_PHY_RFBUS_REQ_EN 0x00000001
38
39#define AR_2040_MODE 0x8318
40#define AR_2040_JOINED_RX_CLEAR 0x00000001 // use ctl + ext rx_clear for cca
41
42#define AR_PHY_FC_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode setting */
43#define AR_PHY_FC_DYN2040_EN 0x00000004 /* Enable dyn 20/40 mode */
44#define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */
45#define AR_PHY_FC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/
46#define AR_PHY_FC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */
47#define AR_PHY_FC_HT_EN 0x00000040 /* ht enable */
48#define AR_PHY_FC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */
49#define AR_PHY_FC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX */
50#define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */
51#define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800
52
53#define AR_PHY_TIMING2 0x9810 /* Timing Control 2 */
54#define AR_PHY_TIMING2_USE_FORCE 0x00001000
55#define AR_PHY_TIMING2_FORCE_VAL 0x00000fff
56
57#define AR_PHY_TIMING_CTRL4_CHAIN(_i) \
58 (AR_PHY_TIMING_CTRL4 + ((_i) << 12))
59#define AR_PHY_TIMING_CTRL4_DO_CAL 0x10000 /* perform calibration */
60#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F /* Mask for kcos_theta-1 for q correction */
61#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0 /* shift for Q_COFF */
62#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0 /* Mask for sin_theta for i correction */
63#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5 /* Shift for sin_theta for i correction */
64#define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800 /* enable IQ correction */
65#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000 /* Mask for max number of samples (logarithmic) */
66#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12 /* Shift for max number of samples */
67
68#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000
69#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000 /* Enable spur filter */
70#define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000
71#define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000
72
73#define AR_PHY_ADC_SERIAL_CTL 0x9830
74#define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000
75#define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001
76
77#define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00
78#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10
79#define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F
80#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0
81
82#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003E0000
83#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17
84#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001F000
85#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12
86#define AR_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000FC0
87#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6
88#define AR_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003F
89#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0
90
91#define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
92#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
93#define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
94#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
95
96#define AR_PHY_EXT_CCA 0x99bc
97#define AR_PHY_EXT_CCA_CYCPWR_THR1 0x0000FE00
98#define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9
99#define AR_PHY_EXT_MINCCA_PWR 0xFF800000
100#define AR_PHY_EXT_MINCCA_PWR_S 23
101#define AR_PHY_EXT_CCA_THRESH62 0x007F0000
102#define AR_PHY_EXT_CCA_THRESH62_S 16
103#define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000
104#define AR9280_PHY_EXT_MINCCA_PWR_S 16
105
106#define AR_PHY_HALFGI 0x99D0 /* Timing control 3 */
107#define AR_PHY_HALFGI_DSC_MAN 0x0007FFF0
108#define AR_PHY_HALFGI_DSC_MAN_S 4
109#define AR_PHY_HALFGI_DSC_EXP 0x0000000F
110#define AR_PHY_HALFGI_DSC_EXP_S 0
111
112#define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0
113
114#define AR_PHY_HEAVY_CLIP_FACTOR_RIFS 0x99ec
115#define AR_PHY_RIFS_INIT_DELAY 0x03ff0000
116
117#define AR_PHY_M_SLEEP 0x99f0 /* sleep control registers */
118#define AR_PHY_REFCLKDLY 0x99f4
119#define AR_PHY_REFCLKPD 0x99f8
120
121#define AR_PHY_CALMODE 0x99f0
122/* Calibration Types */
123#define AR_PHY_CALMODE_IQ 0x00000000
124#define AR_PHY_CALMODE_ADC_GAIN 0x00000001
125#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002
126#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003
127/* Calibration results */
128#define AR_PHY_CAL_MEAS_0(_i) (0x9c10 + ((_i) << 12))
129#define AR_PHY_CAL_MEAS_1(_i) (0x9c14 + ((_i) << 12))
130#define AR_PHY_CAL_MEAS_2(_i) (0x9c18 + ((_i) << 12))
131#define AR_PHY_CAL_MEAS_3(_i) (0x9c1c + ((_i) << 12))
132
133
134#define AR_PHY_CCA 0x9864
135#define AR_PHY_MINCCA_PWR 0x0FF80000
136#define AR_PHY_MINCCA_PWR_S 19
137#define AR9280_PHY_MINCCA_PWR 0x1FF00000
138#define AR9280_PHY_MINCCA_PWR_S 20
139#define AR9280_PHY_CCA_THRESH62 0x000FF000
140#define AR9280_PHY_CCA_THRESH62_S 12
141
142#define AR_PHY_CH1_CCA 0xa864
143#define AR_PHY_CH1_MINCCA_PWR 0x0FF80000
144#define AR_PHY_CH1_MINCCA_PWR_S 19
145#define AR_PHY_CCA_THRESH62 0x0007F000
146#define AR_PHY_CCA_THRESH62_S 12
147#define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000
148#define AR9280_PHY_CH1_MINCCA_PWR_S 20
149
150#define AR_PHY_CH2_CCA 0xb864
151#define AR_PHY_CH2_MINCCA_PWR 0x0FF80000
152#define AR_PHY_CH2_MINCCA_PWR_S 19
153
154#define AR_PHY_CH1_EXT_CCA 0xa9bc
155#define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000
156#define AR_PHY_CH1_EXT_MINCCA_PWR_S 23
157#define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
158#define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16
159
160#define AR_PHY_CH2_EXT_CCA 0xb9bc
161#define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000
162#define AR_PHY_CH2_EXT_MINCCA_PWR_S 23
163
164#define AR_PHY_RX_CHAINMASK 0x99a4
165
166#define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (0x99b4 + ((_i) << 12))
167#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
168#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
169#define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac
170
171#define AR_PHY_EXT_CCA0 0x99b8
172#define AR_PHY_EXT_CCA0_THRESH62 0x000000FF
173#define AR_PHY_EXT_CCA0_THRESH62_S 0
174
175#define AR_PHY_CH1_EXT_CCA 0xa9bc
176#define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000
177#define AR_PHY_CH1_EXT_MINCCA_PWR_S 23
178
179#define AR_PHY_CH2_EXT_CCA 0xb9bc
180#define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000
181#define AR_PHY_CH2_EXT_MINCCA_PWR_S 23
182#define AR_PHY_ANALOG_SWAP 0xa268
183#define AR_PHY_SWAP_ALT_CHAIN 0x00000040
184#define AR_PHY_CAL_CHAINMASK 0xa39c
185
186#define AR_PHY_SWITCH_CHAIN_0 0x9960
187#define AR_PHY_SWITCH_COM 0x9964
188
189#define AR_PHY_RF_CTL2 0x9824
190#define AR_PHY_TX_FRAME_TO_DATA_START 0x000000FF
191#define AR_PHY_TX_FRAME_TO_DATA_START_S 0
192#define AR_PHY_TX_FRAME_TO_PA_ON 0x0000FF00
193#define AR_PHY_TX_FRAME_TO_PA_ON_S 8
194
195#define AR_PHY_RF_CTL3 0x9828
196#define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000
197#define AR_PHY_TX_END_TO_A2_RX_ON_S 16
198
199#define AR_PHY_RF_CTL4 0x9834
200#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF 0xFF000000
201#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24
202#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00FF0000
203#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16
204#define AR_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000FF00
205#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8
206#define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF
207#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0
208
209#define AR_PHY_SYNTH_CONTROL 0x9874
210
211#define AR_PHY_FORCE_CLKEN_CCK 0xA22C
212#define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX 0x00000040
213
214#define AR_PHY_POWER_TX_SUB 0xA3C8
215#define AR_PHY_POWER_TX_RATE5 0xA38C
216#define AR_PHY_POWER_TX_RATE6 0xA390
217#define AR_PHY_POWER_TX_RATE7 0xA3CC
218#define AR_PHY_POWER_TX_RATE8 0xA3D0
219#define AR_PHY_POWER_TX_RATE9 0xA3D4
220
221#define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000
222#define AR_PHY_TPCRG1_PD_GAIN_1_S 16
223#define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000
224#define AR_PHY_TPCRG1_PD_GAIN_2_S 18
225#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
226#define AR_PHY_TPCRG1_PD_GAIN_3_S 20
227
228#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
229#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
230
231#define AR_PHY_VIT_MASK2_M_46_61 0xa3a0
232#define AR_PHY_MASK2_M_31_45 0xa3a4
233#define AR_PHY_MASK2_M_16_30 0xa3a8
234#define AR_PHY_MASK2_M_00_15 0xa3ac
235#define AR_PHY_MASK2_P_15_01 0xa3b8
236#define AR_PHY_MASK2_P_30_16 0xa3bc
237#define AR_PHY_MASK2_P_45_31 0xa3c0
238#define AR_PHY_MASK2_P_61_45 0xa3c4
239
240#define AR_PHY_SPUR_REG 0x994c
241#define AR_PHY_SFCORR_EXT 0x99c0
242#define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F
243#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
244#define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80
245#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7
246#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000
247#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
248#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000
249#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
250#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28
251
252/* enable vit puncture per rate, 8 bits, lsb is low rate */
253#define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18)
254#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18
255
256#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */
257#define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9) /* use mask1 or mask2, one per rate */
258#define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S 9
259#define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100
260#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F
261#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
262
263#define AR_PHY_PILOT_MASK_01_30 0xa3b0
264#define AR_PHY_PILOT_MASK_31_60 0xa3b4
265
266#define AR_PHY_CHANNEL_MASK_01_30 0x99d4
267#define AR_PHY_CHANNEL_MASK_31_60 0x99d8
268
269#define AR_PHY_CL_CAL_CTL 0xA358 /* carrier leak cal control */
270#define AR_PHY_CL_CAL_ENABLE 0x00000002
271#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
272#endif /* _DEV_ATH_AR5416PHY_H_ */
273